Optimized Design of Decoder 2 to 4, 3 to 8 and n to 2n using Reversible Gates

The design of low consumption CMOS circuits, nanotechnologies and quantum computing has becomed more attached to the reversible logic. A set of gates have been recently exploited in reversible computer science for the design of certain circuits. Among them, we find the decoders. In this paper we have exploited a recent study making the design of the decoder 2 to 4, 3 to 8, and n to 2, our work aims to enhance the previous designs , by replacing some reversible gates by others while maintaining their functionality and improving their performance criteria namely the number of gates (CG), number of garbage outputs (NGO), number of constant inputs(NCI), Quantum cost (QC) and hardware complexity (HC), compared to our study of the base and other recent studies from which we have obtained remarkable results. Keywords—Decoder 2to4; Decoder 3to8; Decoder n to2; Number of Gates (CG); Number of Garbage Output (NGO); Number of Constant Inputs (NCI); Quantum Cost (QC); Hardware Complexity (HC)


I. INTRODUCTION
The energy consumed in the circuits presents a major problem revealed in many research studies that are in progress to design low power devices. The loss of energy in static and dynamic electricity consumption within a chip generates thermal dissipation. Moreover, referring to the Landauer principle [1], heat occurs due to the loss of information in any irreversible circuit. The higher the number of information losses, the greater the heat dissipation. In irreversible circuits from the output vector, one cannot uniquely deduce the associated input vector which results in a loss of information which in turn generates a heat dissipation of KTln2Joules by bit loss, where K is the Boltzmann constant and T is the absolute temperature. The amount of heat loss seems small, but it will be large when a circuit contains a good amount of information loss. Bennett [2] in his research has proven that these heat generation problems can be resolved as long as the circuits could be designed with reversibility. There is no loss of information in the reversible circuits, and therefore a minimum amount of power dissipation. Today the need of reversible computing is important. Reversible computation is performed by reversible circuits. A quantum computer is quantum network composed of quantum logic gates; It has applications in many research areas such as Low Power Complementary Metal Oxide Semiconductor (CMOS) design, quantum computing, etc. All quantum gates are reversible gates and therefore quantum computing is one of the ways to design low power circuits. There is a one-to-one mapping of inputoutput model in all quantum gates. Reversible circuits are those circuits whose outputs can be decided from the input template. quantum cost. The pattern of quantum circuit design is to minimize the amount of waste and reduce the quantum cost.
On the other hand [21][22][23] the decrease in energy dissipated at the end of unused bits because heat is directly related to less garbage outputs. This paper will be organized as follows: the 2 n d section presents the reversible gates and their performance criteria, namely the quantum cost deduced from the associated quantum implementation, and the hardware complexity.
In the 3 r d section, we exploit a design of each decoder 2 to 4, 3 to 8, and n to 2 n from a recent article [13] we modify and show their associated performance criteria. To compare our new designs, we expose several designs from previous studies for comparison against our new designs of each decoder in terms of the 5 performance criteria CG, NGO; NCI, QC, and HC.
In the 4 t h section, we will present our design of the decoder 2 to 4, 3 to 8 and n to 2 n and display 5 performance criteria while calculating the percentages of improvement obtained. finally, in the 5 t h section a conclusion and perspectives.

II. THE REVERSIBLE GATES CONCERNED BY THE STUDY AND THEIR PERFORMANCE CRITERIA
In this section we will define the performance criteria concerned by this article which are in total 5.
A. Performance Criteria: 1) Number of Gates (CG): The number of gates required to make a circuit [3].
2) Number of Garbage Outputs (NGO): The unused or unwanted logic outputs of the reversible gate maintain in the output lines to make the circuit reversible [3].

3) Number of Constant Inputs (NCI):
Number of inputs that must be remain constant at 0 or 1 to integrate the given logic function [3].

4) Quantum Cost(QC):
The QC is calculated by counting the number of a one input-output and two input-output reversible gates used in realizing a circuit [4,5]. The QC of a one input-output and two input-output reversible gates is realized to be 1.

5) Hardware Complexity (HC):
The number of fundamental operations (Ex-OR, AND,NO, etc.) required to make the circuit. actually, a constant complexity is supposed for each fundamental operation of the circuit, such as α for Ex-OR, β for AND, δ for NOT, etc. Eventually, the entire number of operations is calculated in terms of α, β, and δ [6].
In this section we will present the reversible gates that are concerned by this paper by showing their performance criteria, namely the quantum cost that we deduce directly from the quantum implementation, and its hardware complexity.
B. Reversible Gates 1) NOT Gate: A reversible gate 1 * 1 having as inputs A and as outputs P = A' the quantum cost of the gate NOT gate is worth QC = 0, its Hardware complexity is worth HC = 1α [3] 2) Feyman Gate FG: A reversible gate 2 * 2 having as inputs A and B and as outputs P = A and Q = A B the quantum cost of the gate FG is worth QC = 1, its Hardware complexity is worth HC = 1α [3] 3) Double Feyman Gate F2G: A reversible gate 3 * 3 having as inputs A , B and C as outputs P = A and Q = A B R= A C the quantum cost of the gate FG is worth QC = 2, its Hardware complexity is worth HC = 2α [3] 4) Fredkin Gate FRG : A reversible gate 3 * 3 figure 1.31 having as inputs A, B and C and as outputs P = A, Q = A'B AC and R = A'C AB the quantum cost of the FRG gate is equal to QC = 2, its Hardware complexity is equal to HC = 2 α + 4 β + 1 δ [3] 5) Peres Gate PG : A reversible gate 3 * 3 figure 1.35 having as inputs A, B and C and as outputs P = A, Q = A and R = AB C the quantum cost of the gate PG is equal to QC = 4, its Hardware complexity is worth HC = 2 α + 1 β [7] 6) RI Gate : A reversible gate 3 * 3 having for inputs A, B and C as outputs P = B, Q = AB'+BC C and R = AB C the quantum cost of the RI gate is equal to QC = 4, its Hardware complexity is worth HC = 1 α+3β+1δ 9) TR Gate : A reversible gate 3 * 3 having for inputs A, B and C as outputs P = A, Q = A B, R = AB' C, S = AB C bigoplus D the quantum cost of the TR gate is equal to QC = 4 and its Hardware complexity is equal to HC = 2 α + 1 β+1 δ [20] 10)DVSM Gate : A reversible gate 4 * 4 having for inputs A, B, C and D as outputs P = AB A'C, Q = AB' A'C, R = A'B AC'and S= D AC A'B' the quantum cost of the TR gate is equal to QC = 11 and its Hardware complexity is equal to HC = 5 α + 7 β+3 δ [11] 11)MFRG1 Gate : A reversible gate 3 * 3 having for inputs A, B and C as outputs P = A, Q = A'B AC', R = A'C AB, the quantum cost of the TR gate is equal to QC = 4 and its Hardware complexity is equal to HC = 2 α + 4 β+2 δ [12] 12)MFRG2 Gate : A reversible gate 3 * 3 having for inputs A, B and C as outputs P = A', Q = A'B AC, R = A'C AB, the quantum cost of the TR gate is equal to QC = 4 and its Hardware complexity is equal to HC = 2 α + 4 β+1 δ [12] 13) OM Gate : A reversible gate 3 * 3 having for inputs A, Band C as outputs P = A, Q = AB C', R = A'B C',the quantum cost of the OM gate is not mentioned in the literature and its hardware complexity is HC = 2 α + 2 β+2 δ [13] 14) SOM Gate : A reversible gate 4 *4 having for inputs A, B, C and D as outputs P = AB C D, Q = AB' C, R = A'B C D S=A'B' C D,the quantum cost of the SOM gate is not mentioned in the literature and its hardware complexity is HC = 5 α + 4 β+2 δ [13] 15) UM Gate : A reversible gate 6 *6 having for inputs A, B, C ,D,E and F as outputs P = A, Q = AB C', R = A'B C' S=A D, T=DE F' and U=D'E F' the quantum cost of the SOM gate is not mentioned in the literature and its hardware complexity is HC = 5 α + 4 β+4 δ [13] 16)RD Gate : A reversible gate 4 *4 having for inputs A, B, C and D as outputs P = AB D, Q = (A+B)' D, R = (A+B') C D S=AB' D, the quantum cost of the RD gate is 8 and its hardware complexity is HC = 5 α + 2 β+2 δ

III. RELATED WORK
In this section, we will present the recent studies of the decoder design : A. Decoder 2 to 4 1) Design1 & Design2: In 2020 Gunajit Kalita [13] proposed 2 decoders designs 2 to 4 as shown in Fig. 1 and 2, respectively . * Design1: The author has used the reversible gate SOM by assigning to the third and fourth input the value 0 so we have CG = 1, NGO = 0, NCI = 2, QC = not mentioned and HC =5 α + 4 β+2 δ * Design2 : The author has used the reversible gate Um by assigning the third and the sixth input the value 1 and at the fourth input the value A and at the fifth input the value B 'so we have CG = 1, NGO = 2, NCI = 4, QC = not mentioned and HC =6 α + 4 β+4 δ  2) Design3 and Design4: In 2013 Lafifa Jamal [9] proposed 2 decoder designs 2 to 4 as shown in Fig. 3 and 4, respectively . * Design 3: The author has used 1 reversible gate FG and 2 reversible gates FRG so we have CG = 3, NGO = 1, NCI = 3, QC = 11 and HC =5 α + 8 β+2 δ

4) Design6:
In 2017 Nazma Tara [10] proposed 1 design of decoder 2 to 4 as shown in Fig. 6. by using 1 reversible gate of the NKHD by assigning to the third input the value 1 and to the fourth, fifth and sixth input the value 0 and concerning its performance criteria we have CG = 1, NGO = 2, NCI = 4, QC = 11 and HC = 6α + 4 β+1 δ 5) Design7: In 2018 Vandana Shukla [11]proposed 1 design of decoder 2 to 4 as shown in Fig. 7. by using 1 reversible gate of the DVSM by assigning to the third and the fourth input the value 0 and concerning its performance criteria we have CG = 1, NGO = 0, NCI = 2, QC = 11 and HC = 5α + 7 β+3 δ 6) Design8: In 2018 G. Greekanth [15] proposed 1 design of decoder 2 to 4 as shown in Fig. 8. by using 2 reversible NOT gates, 2 reversible gates RI by assigning to the 2 third inputs for each the value 0 and concerning its performance criteria we have CG = 2, NGO = 2, NCI = 2, QC = 8 and HC = 2α + 6 β+4 δ
The 2 to 4 reversible decoder circuit is equivalent to fig3 * design4 : Using 1 reversible gate HL by assigning the third input the value 0 and the fourth input the value 1 and the rest of 4 reversible gates FRG by assigning the third input the value 0 so we have CG = 5, NGO = 1, NCI = 6, QC = 27 and HC =15 α + 25 β+7 δ as shown in Fig. 16.
The 2 to 4 reversible decoder circuit is equivalent to fig4.   3) Design5: In 2012 Ravish Aradhya HV [14] proposed 1 decoder designs 3 to 8 by using 7 reversible gates of the FRG, concerning one reversible FRG gate by assigning its second input to the value 1 and the third input to the value 0 and for the rest of the 6 FRG reversible gates, the value 0 is assigned to the third input by concerning its performance criteria we have CG = 7, NGO = 2, NCI = 8, QC = 35 and HC=14 α + 28 β+7 δ as shown in Fig. 17.

4) Design6:
In 2017 Nazma Tara [10]proposed a design of the decoder 3 to 8 using an NKHD reversible gate by assigning to the third input the value 1 and to the fourth, fifth and sixth input the value 0 and 4 FRG reversible gates assigning to the third input for each the value 0 concerning its performance criteria we have CG = 5, NGO = 3, NCI = 8, QC = 31 and HC=14 α + 20β+5 δ as shown in Fig. 18. Fig. 18 shows the 2 to 4 reversible decoder circuit equivalent design shown in Fig. 6.

5) Design7:
In 2018 Vandana Shukla [11] proposed a design of the decoder 3 to 8 using an DVSM reversible gate by assigning to the third and the fourth input the value 1 and for 4 FRG reversible gates assigning to the third input for each the value 0 concerning its performance criteria we have CG = 5, NGO = 1, NCI = 6, QC = 31 and HC=13 α + 23β+7 δ as shown in Fig. 19. 6) Design8: In 2018 G.Sreekanth [15] proposed a design of the decoder 3 to 8 using 6 RI reversible gate by assigning to the third input the value 0 for all gates concerning its performance criteria we have CG = 6, NGO = 3, NCI = 6, QC = 24 and HC=6 α + 18β+8δ as shown in Fig. 20. taking into account 2 NOT used The 2 to 4 reversible decoder circuit is equivalent to Fig.  8.
The 2 to 4 reversible decoder circuit is equivalent to Fig.  9.

8) Design10:
In 2016 Anish Kumar Saha [19] proposed a design of decoder 3 to 8 whose performance criteria are as    [16] proposed a design of decoder 2 to 4 using 3 reversible gate FG, 1 reversible NOT gate, 1 reversible gate PG and 1 reversible gate TR and 4 FRG reversible by assigning to the second input the value 0 gates whose performance criteria are as follows: CG = 10, NGO = 3 , NCI = 7, QC = 31 and HC = 15α + 18 β+6 δ as shown in Fig. 22.
C. Decoder n to 2 n 1) Design1 & Design2: In 2020 Gunajit Kalita [13]proposed 2 decoders designs n to 2 n  * design1 : To build the circuit of the decoder n to 2 n he used a reversible gate SOM and 2 reversible gates UM and assigning to each increment 2 reversible gates Um to each reversible gate UM previous as shown in Fig. 24.

7) Design9:
In 2013 Md. Shamsujjoha [18] proposed n to 2 n using 1 F2G reversible gate and 2 reversible gates FRG ,and assigning to each increment 2 reversible gates FRG to each reversible gate FRG previous as shown in Fig. 30. Concerning the performance criteria we have CG = (2 n )-1 NGO = n, NCI=2 n ,QC=52 n -8 and HC = HC (F2G) + (2 n -2) HC (FRG)= HC=( 2 n+1 -2)α+(2 n+2 -8)β+(2 n -2)δ Limitations of previous studies: We find in these previous studies a certain limitation in terms of less optimized performance criteria, the evidence is that we were able to make our designs with better performance criteria than the previous works while keeping the same functionality.

IV. OUR PROPOSED DESIGN OF DECODER 2 TO 4, 3 TO 8 AND N TO 2 n
In this paragraph we will present our circuits concerning the decoder 2 to 4, 3 to 8 and n to 2 n Our work is based on the article [13] ,we try to modify it to improve certain performance criteria, starting with:

A. Decoder 2 to 4
We thought of exploiting its circuit 2 to 4 [13] by replacing the reversible gate SOM by that of the RD and to assign to the third and fourth input the value 0 Fig. 31 shows our design of decoder 2 to 4.
Concerning the performance criteria of our design we have CG=1,NGO=0 ,NCI)2,QC=8 et HC= 5 α + 2 β+2 δ B. Decoder 3 to 8 After using the decoder circuit 3 to 8 of the [13], the reversible gate SOM has also been replaced by that of the RD, and the 2 reversible gates UM by 4 reversible gates RI. The performance criteria obtained are as follows: CG=5,NGO=1,NCI=6 ,QC=24 and HC=9α + 14 β+6 δ C. Decoder n to 2 n Our conception of decoding n to 2 n is done by adopting our decoder circuit 3 to 8 by adding to each reversible gate RI 2 reversible gates RI. Fig. 33 shows our design of the decoder n to 2 n .
The performance criteria obtained are as follows: Concerning the performance criteria we have as follows: 1) lemma 1: CG = 2 n -3 Proof: we will demonstrate it recurrently for n = 2 we have CG = 2 2 -3 =4-3= 1 that's correct because we have only one reversible gate which is RD.
Suppose that for n-1 we have CG = 2 n − 1 -3 and prove for n we have CG = 2 n -3 for n on CG = 2 n−1 -3+ 2 n−1 because the n th column of the reversible gates RI we have in total 2 n − 1 therefore CG = 2 *2 n−1 -3 = 2 n -3 so it's correct then CG = 2 n -3 2) lemma 2: * NGO = n-2 Proof: we will demonstrate it recurrently for n = 2 we have NGO = 2-2 = 0 that's correct because the RD reversible gate has no garbage output.
Suppose that for n-1 we have NGO = n-1-2 =n-3 and prove for n we have NGO = n-2 for n on NGO = n-3+1 =n-2 because at the n th column of the RI reversible gates there is only one garbage output so it's correct then NGO = n-2 3) lemma 3: * NCI = 2 n -2 Proof: we will demonstrate it recurrently for n = 2 we have NCI = 2 2 -2 = 2 that's correct because the RD reversible gate has 2 constants inputs.
From these results we draw up our Table 3.10 based on which we can present the graph containing the performance criteria in the form of bars Fig. 34.   Based on the results obtained in the recent table, we were able to reduce in terms of: -Number of gates: 28.57 % with respect to design3 [9], design [14], design [12], 50 % with respect to design [19], design [16], design [18] and 16, 67 % compared to design [15].
Then this table represents the performance criteria of each design of decoder n 2 n and the % improvement in terms of these of our design compared to recent decoders, all of these parameters of which are expressed as a function of n.
In the column of % improvement of HC we represent respectively our percentages of CNOT, AND and NOT which are separated by the symbol -.
After having presented the improvements obtained from our design of the decoder n at 2n in terms of performance criteria, we will assume that n tends to infinity in order to be able to give improvements of % and therefore to obtain the following Table IV. Then when n tends to infinity we obtain the following improvements according to each performance criteria: -Number of garbage outputs: 100% compared to design 1 [13].

VI. CONCLUSION
Reversible logic occupies a important role in minimizing energy loss at the end of unused bits in the circuit compared to conventional logic computation.Our designs were able to minimize all performance criteria Number of gates CG, Number of constant inputs NCI, Quantum Cost QC, Hardware Complexity HC and especially the number of garbage outputs NGO in our design 2 to 4, 3 to 8, and n to 2 n , as a result a decrease in the energy dissipated at the end of unused bits because heat is directly related to fewer garbage outputs. While waiting for new reversible gates to exploit in the future, we can optimize decoder 2 to 4, 3 to 8, and n to 2 n respecting the performance, typically concerning minimizing heat energy.