Design of a High Performance Low-power Consumption Discrete Time Second Order Sigma-delta Modulator Used for Analog to Digital Converter

—This paper presents the design and simulations results of a switched-capacitor discrete time Second order Sigma-Delta modulator used for a resolution of 14 bits Sigma-Delta analog to digital converter. The use of operational amplifier is necessary for low power consumption, it is designed to provide large bandwidth and moderate DC gain. With 0.35µm CMOS technology, the ΣΔ modulator achieves 86 dB dynamic range, and 85 dB signal to noise ratio (SNR) over an 80 KHz signal bandwidth with an oversampling ratio (OSR) of 88, while dissipating 9.8mW at ±1.5V supply voltage.


INTRODUCTION
Analog to digital converters (ADC) with high resolution are widely used in the areas of instrumentation, measurement, telecommunications, digital signal processing, consumer electronics, etc.With the advancements in the Very Large Scale Integration (VLSI) technologies, the focus is shifted on oversampling and ΔΣ converters for applications requiring high precision analog-to digital conversion with narrow bandwidth [1,2,3,4].They are preferred because of their inherent relaxed sensitivity to analog circuit errors and reduced analog processing as compared to other analog-to-digital conversion techniques.These advantages come at the expense of relatively large amount of digital processing and the working of the majorpart of circuit at a clock rate which is much higher than the analog-to-digital conversion rate.Because of using higher clock rates and feedback loop, these converters tend to be robust in the face of analog circuit imperfections [3] and do not require trimmed components which are considered necessary in conventional high precision Nyquist rate ADCs.
For these reasons, high precision ΔΣ ADCs can be implemented using high density VLSI processes.ΣΔ ADC is a system which consists of a ΣΔ modulator followed by a digital decimation filter.The ΣΔ modulator oversamples the input signal i-e performs sampling at a rate much higher than the nyquist rate.The ratio of this rate to the Nyquist rate is called over-sampling ratio (OSR).
After over-sampling, it typically performs very coarse analog-to-digital conversion at the resulting narrow-band signal.By using coarse digital-to-analog conversion and feedback, the quantization error introduced by the coarse quantizer is spectrally shaped i-e the major portion of the noise power is shifted outside the signal band.This process is called quantization noise shaping.The digital decimation filter removes the out-of-band portion of the quantization error and brings back the output rate to Nyquist rate.
The paper is organized as follows.Section II presents a review of ΣΔ modulator with theoretical analysis.Section III presents the described structure of the second order ΔΣ modulator with simulations results.In section IV, all main parameters of the proposed modulator are indicated with a full comparison of the most popular designs in which the performance of each modulator is cited in table IV.Conclusion is drawn in Section V.

II. REVIEW OF SIGMA-DELTA MODULATOR
Signal-to-noise ratio (SNR) and Dynamic range (DR) are two most important specifications commonly used to characterize the performance of over-sampling sigma-delta ADCs [5].The system design begins with the calculation of the dynamic range.According to the design theory, the DR of a sigma-delta modulator can be gotten by following formula.


The theoretical DR is a function of the modulator order L, oversampling ratio OSR, and the numbers of bits in the quantizer B.
The expression (1) reveals that an additional bit in the internal quantizer can roughly obtain a 6-dB improvement of DR.This improvement is independent of the OSR, while the improvement obtained with increasing the order L is dependent on it.The DR of a theoretical L th-order Sigma-Delta converter increases with OSR in (L + 1/2) bits/octave.This is shown in Figure 1, where the DR is plotted as a function of the oversampling ratio and the modulator order, in case of a singlebit internal quantizer.www.ijacsa.thesai.orgThe SNR of a converter is the ratio of the input signal power to the noise power measured at the output of the converter.The maximum SNR that a converter can achieve is called peak signal-to-noise-ratio (SNR p ).The noise here should include the quantization and circuit noise.The SNRP of the Lth order Sigma-Delta modulator can be calculated as:


The SNR of the ΣΔ ADC can be increased by (2L + 1) 3dB, or L + 0,5bits by doubling the oversampling ratio, where L denotes the order of the loop filter.It is tempting to raise the oversampling ratio to increase the SNR of the Sigma-Delta modulator.However, it is restricted by the speed limit of the circuit and the power consumption.
In practice, for the same performance, it is preferred to lower the oversampling ratio.Another driving force is the ever increasing bandwidth requirement, which also needs to lower the oversampling ratio.
For high bandwidth converters, the oversampling ratio should be kept as low as possible.A lot of efforts have been made at the system level to lower the oversampling ratio and maintain the same performance.
Starting from the desired 14-bit of resolution, the Sigma-Delta ADC was designed.The DR is computed as follows: Where N represents number of bits, hence DR (dB) is equal to 86.04dB.For computing the OSR for first, second and third order devices, a small MATLAB script was developed using the following equation: If we choose an OSR equal to 88, F s is the sampling frequency which is calculated to 14.08MHz, and f b means base band frequency (80 KHz).Table I shows the results of the equation ( 4) for a first, second and third order.For a first order modulator an OSR of 960 is needed, given a relatively high sampling frequency for the 0.35µm CMOS ultra-low-voltage system.For the second and third order devices, better sampling frequencies are required.Although for the third order modulator, the lowest sampling frequency is needed, this frequency implies the use of higher consumption and taking up more area.For that reason, a second order modulator was chosen for this application.
N is the effective number of bits of ΔΣ converter which is given by [6]: Where B represents number of bits of the quantization circuitry (B = 1).
In this case, OSR is equal to 88, F s is the sampling frequency which is calculated to 14.08MHz.We obtained an effective number of bits equal to 14 bits which verify the two last results in equations ( 1 As shown in figure 2, first-order ΣΔ modulator has the advantages of being simple, robust and stable.Despite these good points, its overall performance in terms of resolution and idle-tone generation is inadequate for most applications.Second-order ΣΔ modulator overcomes these disadvantages at the expense of increased circuit complexity and reduced signal range.According to figure 2, the modulator can be considered as a two-input [E (z) and X (z)], one-output [Y (z)] linear system.The output signal is expressed as: Where STF (z) is the signal transfer function and NTF (z) is the noise transfer functions, which are given by:  By using superposition principle, the output signal is obtained as the combination of the input signal and the noise signal, with each being filtered by the corresponding transfer function: In this case, the output signal for the ideal linear model can be written as: To achieve the objective cited above, All main parameters of the described modulator are summed up in Table II.The functional diagram of the second order modulator simulated using Simulink in MATLAB is shown in Figure 3.The single bit DAC is replaced by a simple wire.The input is a sinusoidal signal with 0.4 V amplitude and frequency 20 kHz.This signal is fed through two integrators and is connected to the comparator at the output.The modulated output as seen through the scope is shown in Figure 4 with the input signal overlaid on it.A discrete Fourier Transform (DFT) of the sampled output signal is performed to calculate the SNR of the system.The logarithm of the amplitude of the signal is plotted versus the signal frequency and the SNR is found to be close to 85.17 dB as shown in Figure 5.It can be seen that second order noise shaping is taking place wherein most of the noise is pushed to the higher frequency bands as shown in figure 6.The original signal can be retrieved using a digital low pass filter.As shown in figure 7, signal sampling is completed by the first integrator connecting to the input.For this reason, the amplifier determines the whole performance of the sigma-delta modulator and needs to be carefully designed.Each integrator is made up of one operational amplifier.This operational amplifier has an adequate bandwidth and higher voltage gain.It is composed of two input transistors formed by P-channel MOSFETs M1 and M2 in order to reduce 1/f noise [7].This stage of op-amp is also formed by N-channel MOSFETs, M3 and M4.The use of transistor M7 as a Pchannel common source amplifier forms the second stage of op-amp.The polarisation block is formed by ten transistors (M5, M6, M8, M9, M10, M11, M12, M13, M14 and M15) with variable input voltage V in and input resistance R in .
The overall gain of the amplifier is found to be given by:     Where g mi is the transconductance and r dsi is the drain to source resistance of i th transistors with i =1,2,4,6,7.Considering the appeal to moderate speed and noise of operational amplifier together with the low power consumption of the operational amplifier, Miller structure is chosen, and the structure of circuit is shown in figure 8.The system has problems of instability because the signal will pass through two-stage circuit and may bring extra pole and zero in this operational amplifier, so it requires importing frequency compensation.Simulations results using T-spice shows that output frequency response of our operational amplifier achieves a gain of 60 dB with a large gain bandwidth of 82 MHz and a phase margin of 62° to ensure more stability (figure 9).www.ijacsa.thesai.org

A. Why high performance and low power?
With the rapid development of computers and communications, a very large number of chips required to have higher performance, low power and small size.Hence analogue, mixed signals with low power and especially Sigma-Delta modulators become more and more important.Operational amplifier structure for almost all modulators circuits determine the performance of analogue structure, which largely depends on their characteristics.One of the popular op-amp is a two-stage Miller op-amp.It introduces an important concept of compensation.The object of this compensation is to maintain stability of the operational amplifier.This last is made up of three stages even though it is often referred to as a "two-stage" op-amp, ignoring the buffer stage.The first stage is composed of the input devices of the differential pair which are formed by P-channel or N-channel MOSFETs.It plays a very important role due to its differential input to single-ended output conversion and its high gain.In addition this stage of op-amp also had the current mirror circuit formed by N-channel MOSFETs.In the other hand the second stage is formed by only one transistor which serves as a Pchannel common source amplifier.The current I bias of the opamp circuit goes through current mirrors formed by the rest of P-channel transistors in order to produce a low current of 10µA [17].
According to figure 10, the DC characteristic for the V-I converter for different values of resistance (R out =100 Ω, R out =2.5 KΩ, R out =5 KΩ) is presented.In the one hand the full input voltage swing capability is evident with truly linearity.In the other hand, in order to ensure low and low consumption an input voltage V in varied from -1.1V to 0V to provide a current from -10µA to 150µA.In this case the current is equal to 10µA at input voltage V in equal to -1V.From figure 8, the Miller operational amplifier is presented.
Here in the polarisation circuit, an amplifier between the mirror's input and output transistor is necessary to achieve high current copy accuracy.In the other hand we use a simple amplifier composed of only two transistors.This amplifier is proposed by K. Tanno [19] to provide low voltage, low consumption and high performance as shown in figure 11.  [18] (b)Two-transistor amplifier structure [19]

Figure 2 .
Figure 2. Linear model of conventional first order ΣΔ Modulator

Figure 3 .
Figure 3. Block diagram of Second Order ΣΔ Modulator

Figure 4 .
Figure 4. Pulse density output from a sigma-delta modulator for a sine wave input

FrequencyFigure 5 .
Figure 5. Frequency spectrum zoom of the modulated signal

Figure 6 .Figure 7
Figure 6.Frequency spectrum of the modulated signal Figure 7 shows a block diagram of a complete Secondorder ΣΔ modulator.It is made up of two integrators, a comparator, and digital to analog converter (DAC).These include switches Q and Q' for applying one of two reference node voltages, +V ref and -V ref , depending on comparator output polarity.The two integrators are based on amplifier, and use two phase, with the respective phases denoted by ɸ1 and ɸ2.

Figure 9 .
Figure 9. Frequency response of Operational Transconductance Amplifier

Figure 10 .
Figure 10.DC characteristics of V-I converter for different values of resistance Rout

TABLE I .
OSR FOR FIRST TO THIRD MODULATOR'S ORDER

TABLE II .
DESIGNED MODULATOR PARAMETERS