Assistant Professo

In this paper, we proposed an area-efficient carry select adder by sharing the common Boolean logic term. After logic simplification and sharing partial circuit, we only need one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation. Through the multiplexer, we can select the correct output result according to the logic state of carry-in signal. In this way, the transistor count in a 32-bit carry select adder can be greatly reduced from 1947 to 960.


INTRODUCTION
The carry-ripple adder is composed of many cascaded single-bit full-adders.The circuit architecture is simple and area-efficient.However, the computation speed is slow because each full-adder can only start operation till the previous carry-out signal is ready.In the carry select adder, N bits adder is divided into M parts.Each part of adder is composed two carry ripple adders with cin_0 and cin_1, respectively.Through the multiplexer, we can select the correct output result according to the logic state of carry-in signal.The carry-select adder can compute faster because the current adder stage does not need to wait the previous stage's carry-out signal.The summation result is ready before the carry-in signal arrives; therefore, we can get the correct computation result by only waiting for one multiplexer delay in each single bit adder.
In the carry select adder, the carry propagation delay can be reduced by M times as compared with the carry ripple adder.However, the duplicated adder in the carry select adder results in larger area and power consumption.In this paper, we proposed an area-efficient carry select adder by sharing the common Boolean logic term.After Boolean simplification, we can remove the duplicated adder cells in the conventional carry select adder.Alternatively, we generate duplicate carryout and sum signal in each single bit adder cell.By utilizing the multiplexer to select the correct output according to its previous carry-out signal, we can still preserve the original characteristics of the parallel architecture in the conventional carry select adder.In this way, the circuit area and transistor count can be greatly reduced and power delay product of the adder circuit can be also greatly lowered.The research efforts of the past years in the field of digital electronics have been directed towards the low power of digital systems.Recently, the requirement of probability and the moderate improvement in battery performance indicate power dissipation is one of the most critical design parameters day by day the demand of probability and mobility is increasing.Also the area of chip design is taken into consideration while talking about probability.Hence three most widely accepted parameters to measure the quality of a circuit or to compare various circuit styles are area, delay and power dissipation.There are three major sources of power consumption in digital CMOS circuits, which are summarized in the following equation [I].P total = P switching + P short-circuit + P leakage = (α 0→1 x C L x V dd 2 x f clk ) + (I sc x V dd ) + (I leakage x V dd ) The first term represents the switching component of power, where C is the load capacitance, f clk is the clock frequency and α 0→1 is the node transition activity factor.The second term is due to the direct path short circuit currents, I sc , which arises when both the NMOS and PMOS transistors are simultaneously active, conducting current directly from supply to ground.Finally, leakage current, I leakage , which can arise from substrate injection and sub threshold effects, is primarily determined by fabrication technology considerations.However, while supply voltage reduction is the most effective way to reduce the power consumption, such a reduction require new design methods for low-voltage and low power integrated circuits.Since an average of 15-20% of the total power is dissipated in glitching, low power can also be achieved by reducing the glitches of the circuit [l].

II. AREA-EFFICIENT CARRY SELECT ADDER
The carry ripple adder is constructed by cascading each single-bit full-adder [1].In the carry ripple adder, each fulladder starts its computation till previous carry-out signal is ready.Therefore, the critical path delay in a carry ripple adder is determined by its carry-out propagation path.The critical path is N-bit carry propagation path in the full-adders.As the bit number N increases, the delay time of carry ripple adder will increase accordingly in a linear way.www.ijacsa.thesai.org In order to improve the shortcoming of carry ripple adder to remove the linear dependency between computation delay time and input word length, carry select adder is presented [2].The carry select adder divides the carry ripple adder into M parts, while each part consists of a duplicated (N/M)-bit carry ripple adder pair.This duplicated carry ripple adder pair is to anticipate both possible carry input values, where one carry ripple adder is calculated as carry input value is logic "0" and another carry ripple adder is calculated as carry input value is logic "1".When the actual carry input is ready, either the result of carry "0" path or the result of carry "1" path is selected by the multiplexer according to its carry input value.To anticipate both possible carry input values in advance, the start of each M part carry ripple adder pair no longer need to wait for the coming of previous carry input.As a result, each M part carry ripple adder pair in the carry select adder can compute in parallel.In this way, the critical path of N bit adder can be greatly reduced.In the conventional N-bit carry ripple adder design, the critical path is N-bit carry propagation path plus one summation generation stage.Alternatively, the critical path is (N/M)-bit carry propagation path plus M stage multiplexer with one summation generation stage in the N-bit carry select adder.Since M is much smaller than N and delay in the multiplexer is smaller than that in the full adder, the computation delay in the carry select adder is much shorter than that in the carry ripple adder.However, implementing the adder with duplicated carry generation circuit costs almost twice hardware and twice power consumption as compared with the carry ripple adder.Therefore, in this paper, we proposed an area-efficient carry select adder by sharing the common Boolean logic term to remove the duplicated adder cells in the conventional carry select adder.In this way, we can save many transistor counts and achieve a lower PDP As compared with the conventional carry select adder, our speed is a little slower since the parallel path in our design is shorter.However, we can achieve lower area, lower power consumption, and lower PDP.As compared with the carry ripple adder, our speed can be faster because some of the parallel architecture in the conventional carry select adder is retained.The delay time in our proposed adder design is also proportional to the bit number N; however, the delay time of multiplexer is shorter than that of full adder.
Consequently, our area-efficient adder can perform with nearly the same transistor count, nearly the same power consumption, but with faster speed and lower PDP as compared with the carry ripple adder

III. SIMULATION COMPARISON RESULTS
We compare the circuit performance with three different architectures, 32-bit carry ripple adder, 32-bit carry select adder, and 32-bit area-efficient carry select adder that is proposed in this paper.As for the transistor count, the transistor count of our proposed area-efficient carry select adder could be reduced to be very close to that of carry ripple adder; however, the transistor count in the conventional carry select adder is nearly double as compared with the proposed design.This result shows that sharing common Boolean logic term could indeed achieve a superior performance in aspect of transistor count.
The area-efficient carry select adder can also achieve an outstanding performance in power consumption.Power consumption can be greatly saved in our proposed areaefficient carry select adder because we only need one XOR gate and one INV gate in each summation operation as well as one AND gate and one OR gate in each carry-out operation after logic simplification and sharing partial circuit.Because of hardware sharing, we can also significantly reduce the occurring chance of glitch.Besides, the improvement of power consumption can be more obvious as the input bit number increases.We simulated the power consumption in the proposed area-efficient adder and the conventional carry select adder with 4, 8, 16, and 32-bit respectively in tsmc 0.18um CMOS technology.The power consumption difference between these two designs is small in the case of 4-bit input word length.Since the conventional carry select adder consists of the duplicated adder cells to prepare both the possible output values for the corresponding carry input values in advance.It not only needs larger hardware area, but also generates more glitch signals because of propagation path difference.
Therefore, as the input bit number increases, the slope of power consumption increase in the conventional carry select adder would be larger than that in our proposed design.As the input bit number of the conventional carry select adder increases to 32-bit, the power consumption in the conventional carry select adder will be 3.3 times larger than that in our proposed area-efficient carry select adder.
The conventional carry select adder performs better in terms of speed.The delay of our proposed design increases slightly because of logic circuit sharing sacrifices the length of parallel path.However, the proposed area-efficient carry select adder retains partial parallel computation architecture as the conventional carry select adder design; the delay increment of the proposed design is similar to that in the conventional design as the input bit number increases.We also simulated the delay performance in the proposed area-efficient adder and conventional carry select adder with 4, 8, 16, and 32-bit respectively.www.ijacsa.thesai.orgThe delay difference existing between these two designs is mainly come from the length difference in their parallel paths.In the conventional carry select adder, it divided N bits into M blocks; however, our proposed design divided every single bit as individual block.In other words, we still retain N blocks in the N bits adder.Such arrangement will lead to some speed sacrifice.We further analyze the Power-Delay-Product as shown.
The proposed area-efficient carry select adder is constructed by sharing the common Boolean logic term in summation generation.
We can find out that the PDP of our proposed design is smaller as compare with the conventional carry select adder and carry ripple adder design.The difference of PDP between these three designs is small in the case of the smaller input bit number.
However, as the input bits increases, the slope of power consumption increment in the conventional carry select adder would be larger than that of the proposed design.Our proposed design can compute the addition function more efficiently by means of logic circuit sharing and partial parallel computation architecture retaining; therefore, the power saving ratio in our design would be much higher than the ratio of speed sacrifice.Simplifying the carry select adder through logic simplification and partial logic circuit sharing can make the carry select adder more area-efficient and more power-efficient.The performance index of transistor count, power, delay, and PDP are summarized in Table 1.
As compared with the carry ripple adder, operation speed in our proposed carry select adder can be much faster; however, transistor count and power consumption only increase slightly.In the case of a 32-bit adder, the transistor count in the carry ripple adder is 896.The transistor count in our proposed area-efficient carry select adder is 960, which only increases 7%.
However, the transistor count in the conventional carry select adder is 1974, which increases more than twice.In terms of power consumption, we can save much power through removal of redundant logic and redundant signal switching by means of sharing common Boolean logic term.As compared with the conventional carry select adder, we can save 70% power.Relative to the carry ripple adder, we only increase 2% power.As a result, our proposed area-efficient carry select adder can perform the lowest PDP, which is only 60% of conventional carry select adder and 66% of carry ripple adder, respectively

IV. RESULTS
The result is carried out at 1.8v supply voltages and average powers consumed and delay at sum and carry output are finding out In this paper, an area-efficient carry select adder is proposed.By sharing the common Boolean logic term, we can remove the duplicated adder cells in the conventional carry select adder.In this way, the transistor count in a 32-bit carry select adder can be greatly reduced from 1947 to 960.Moreover, the power consumption can be reduced from 1.26mw to 0.37mw as well as power delay product reduced from 2.14mw*ns to 1.28mw*ns.By retaining part of parallel architecture of conventional carry select adder, we can still maintain some competitiveness in speed.In this way, our areaefficient adder can perform with nearly the same transistor count, nearly the same power consumption, but with faster speed and lower PDP as compared with the carry ripple adder.M odul e0

Figure 1 .
Figure 1.The N-Bit Carry Ripple Adder Constructed By N Set Single Bit Full-Adder

Figure 2 .
Figure 2. The 16-Bit Carry Select Adder Is Divided By The Carry Ripple Adder Into 4 Parts, While Each Part Consists Of A Duplicated 4-Bit Carry Ripple Adder Pair.

TABLE I .
PERFORMANCE Parameters Of 5 Bit Carry Select Adder www.ijacsa.thesai.org