ROI-based Compression on Radiological Image by Urdhva-Tiryagbhyam and DWT Over FPGA

The area of radiological image compression has not yet met its potential solution. After reviewing the existing mechanism of compression, it was found that majority of the existing techniques suffers from significant pitfalls e.g. more usage of transformation schemes, more resource utilization, delay, less focus on FPGA performance enhancement, extremely less emphasis on Vedic-multipliers. Hence, this paper presents an analytical modelling of ROI (Region of Interest)-based radiological image compression that applies Vedic Multiplier Urdhva-Tiryagbhyam to enhance the performance of coding using Discrete Wavelet Transform (DWT). The study outcome was implemented in Matlab and multiple test bed of FPGA devices (Virtex 4 FX100 -12 FF1152 and Spartan 3 XC4005TQ144) and assessed using both visual and numerical outcomes to find that proposed system excel better performance in comparison to recently existing techniques. Keywords—Radiological Image Compression; Discrete Wavelet Transform; FPGA; Lifting Scheme


INTRODUCTION
With the advancement of radiological image processing, the area of healthcare and the diagnostic sector has been imparted with various means to visualize the diseases with higher accuracies.Various kinds of radiological imaging systems e.g.Ultrasound, Positron Emission Tomography, Computed Tomography scans, Magnetic Resonance Imaging, have assisted radiologist and physician to investigate the disease very closely [1].With the evolution of cloud, storage is never a problem and hence the adoption of cloud or any pervasive computing significantly assists in storing such radiological images.However, there is a darker side of this story even at present about radiological image.Normally, radiological images are very different from other types of images in the form of information contents.A normal MRI image can be around 5-6 MB, whereas the size can further increase [2].Although storage is not a problem, a problem arises in particular applications e.g.telemedicine, robotic surgery, etc. [3][4] [5].In such applications, it is required that a bigger size of the image may need to be transferred from one to another end of the world with least delay as possible [6].There are many network parameters e.g.traffic congestion, channel capacity, interference, noise that always affects the transmission [7], which is less likely to be controlled.However, a better transmission of a radiological image will also require that image retains its maximum signal quality which will degrade in the process of transmission.The solution of all this is an effective compression algorithm.An effective compression algorithm not only reduces the size but also ensures to retain maximum signal quality while reconstructing it at the end receiver [8].At present, there are various lossless and lossy compression schemes [9] to accomplish maximized compression ratio, but the biggest challenge of lossy schemes is to recover the original data.On the other hand, usage of lossless compression schemes minimizes the compression ratio although it has the potential to recover the complete data.The significant problem is that lossless scheme is the only alternate solution in radiological image compression as it can't allow losing any forms of clinical information at any cost.Another problem is that bigger images e.g.MRI images has a bigger background which is not required to be processed at all as it occupies half of proportion size of the entire image resulting in the expensive matter.Moreover, such null background also has artifacts as well as noise during the process of acquisition of an image.Hence, implementation of denoising techniques further degrades the signal quality [10].At present, there is an increasing trend of using JPEG2000 standards owing to its supportability of advanced characteristics of radiological image processing.It is found to have an optimal efficiency of coding in comparison to conventional compression scheme [11].JPEG2000 also has higher supportable features of Discrete Wavelet Transform (DWT) along with various arithmetical schemes of coding [12].There is an increasing attention from the research community towards using DWT-based scheme and its associated architecture.It was also found that FPGA has enough potential to hone the potential features of DWT.There have been a various research attempts on using FPGA and DWT together in image processing [13].All these implementations suffer from certain flaws e.g. more dependencies on control signals, inferior hardware utilization, more latency, increasing demands of registers in hardware design, etc.This paper introduces a technique that jointly uses Vedic Multiplier, FPGA (Field Programmable Gate Array), lifting scheme, and DWT (Discrete Wavelet Transform) to overcome the problems.Section II discusses the existing research work towards the topic followed by a briefing of problem identification in Section III.Section IV introduces the adopted methodology of proposed system followed by a discussion of algorithms in Section V. Result accomplished from the study is discussed in section VI followed by a summary of the work in conclusion under Section VII.

II. RELATED WORK
This section discusses the techniques adopted for radiological image compression during the year 2010-2015.www.ijacsa.thesai.orgDiscrete Cosine Transform is one of the most frequently used compression algorithm for images.The work carried out by Dhandapani and Ramachandran [14] have presented an 8x8 transformation matrix needed by an added and thereby skipping shift and multiplication using FPGA.Although, the outcome was found to exhibit power effectiveness with lesser delay compared to other existing system but it doesn't prove computational efficiency.Another frequently used technique to perform compression is DWT and SPIHT (Set-Partitioning in Hierarchical Trees).Fang et al. [15] have introduced a unique interpolation-based scheme using Lagrangian theory in to show better supportability of prediction depending upon local features.The study outcome was found to minimize execution time along with the length of coding bits but was not found to offer better signal quality of reconstructed image.Usage of DWT for radiological image compression was also seen in the work of Govindan and Sanile [16], where it was used for truncating the sub-bands in ultrasonic images.The authors have also applied interpolation technique using Fourier transform to obtain enhanced signal quality.The study has used both spatial and temporal correlational properties in to perform compression.The study outcome was assessed to find better signal quality (measured by PSNR), correlational coefficient, and quality of reconstruction, computational speed, and resource utilization.However, the technique was not found benchmarked.Same authors [17] have extended the similar work using system-on-chip platform using OpenCL language over GPU.Medical images are not only limited to radiological images, but there are also other forms of it.One of such form is DNA microarray, which is frequently used in genetic engineering.Cabronero et al. [18] have particularly addressed the problem of compressing such medical image of DNA microarray using a quantization-based approach.The contribution of the work is to restrict the relative error due to quantization.On increasing bitrates, the study was found to have better error control.Rehman et al. [19] have presented a discussion on bi-orthogonal transform.The technique takes the input image and converts it to macro blocks which are then further transformed into blocks and pixels.The authors have used JPEG XR to perform compression with lowered memory usage.Yoon et al. [20] have applied L-fold down sampling to minimize the coefficients of filters and data rates.
Apart from transform-based implementation techniques, there is a frequent usage of FPGA-based schemes too for performing compression.Ahmad et al. [21] have introduced a three-dimensional daubechies for compressing the medical image.The three dimensionalities are achieved by considering two transpose buffers and one-dimensional Daubechies.The study outcome was found with lower consumption of power but without benchmarking.Anjaneyulu and Krishna [22] have used conventional DWT as well as SPIHT on FPGA.However, this work is a replica of original work carried out by Fang et al. [15] and doesn't show many novel features in work.Usage of FPGA was also advocated by Botella et al. [23].In existing system, FPGA was used in a different way too.For example, the work carried out by Li et al. [24] has developed a synthesis tool using FPGA.However, the study didn't provide enough evidence to claim its effectiveness.Nagabhushanam et al. [25] has also used FPGA-based approach and DWT-based scheme to perform image compression.The authors have addressed the complexity of DWT by incorporating the enhanced version of DWT using distributive arithmetic.The study outcome was found with lowered latency and increased throughput regarding clock cycles.However, the outcome didn't studied computational complexity.Wu et al. [26] have applied SPIHT along with FPGA to perform image compression.The technique incorporates parallelism over SPIHT algorithm to enhance the processing capacity.The basic technique is to retain the maximized PSNR and minimize the storage demands.However, the technique is not cost effective if the dataset is changed to complex medical image.Xuesen et al. [27] have designed an experimental test-bed that uses FPGA for investigating the acquired data from the medical image.Among all these techniques, the performance of the system can be greatly enhanced if a suitable multiplier is applied to maintain a balance between compression and quality of the reconstructed image.In this regards, Vedic-based multipliers designs have also been researched to some extent.Most recently, Arish and Sharma [28] have presented a design of multiplier for floating point that significantly controls both power dissipation and delay.The authors have used two Vedicbased schemes e.g.Urdhva-Tiryagbhyam algorithm and Karatsuba algorithm to deploy binary multiplier of the unsigned type for the purpose of carrying out mantissa multiplication.An exactly similar version of work is also carried out by Kodali et al. [29] in the same year.Usage of Vedic mathematics was found in work carried out by Pohokar et al. [30].The work was carried out in FPGA and outcomes are found with reduced delay and memory demands compared to the traditional multiplier.Nearly similar work was also carried out by Sharma and Goyal [31] most recently only with a difference that actual work of Pohokar [30] was implemented in FPGA in 2015 and same work was also published by Sharma and Goyal [31] in H-Spice in 2016.Singh and Sasamal [32] have presented a study where binary Vedic multiplier is implemented over cadence tool using adiabatic logic.Usage of another Vedic sutra called as Calana Kalanabhyam was seen in the work of Verma et al. [33] where the authors have used it alongside with FPGA to make energy-efficient sutra.Vijayan et al. [34] have presented a Vedic multiplier of 8-bits in FPGA.Hence, it can be seen that there are quite a lot of study being carried out on the topic of image compression using DCT, Fourier transforms, FPGA, Vedic multiplier, SPIHT, etc.All the studies have significant points to learn as well as pitfalls too.The Vedic multiplier, although being an older concept, has not been much explored in the area of medical image compression.The next section elaborates about the problems being identified from the existing studies.

III. PROBLEM IDENTIFICATION
This section discusses the problem identification after reviewing the literature from the existing system:  More inclination towards transformation-based schemes: It has also been seen that transformation based schemes (e.g.DWT, DCT, SPIHT) are more used for performing compression.However, there is some potential trade-off in using such schemes which were completely not highlighted in any of the research work till date.Although wavelet-based schemes www.ijacsa.thesai.orgsupport compression of both lossy and lossless image, unfortunately there are many modalities that are found not support the generation of compressed objects in JPEG2000 [35].Existing techniques doesn't addressed a problem that compressed JPEG2000 objects are not supported by Picture Archiving And Communication System (PACS) that forces converting the image to some other formats while transmission.Moreover, usage of the wavelet-based scheme includes higher computational cost [35].
 Less focus on enhancing FPGA: At present, there are many FPGA-based schemes using radiological image processing.However, the biggest research gap is FPGA is just used as a platform for synthesis.For example, the work carried out by various researchers [24][25] [26] have used FPGA using an image.However, it was totally ignored that image conversion module over various devices of FPGA includes various steps that are a computationally intensive process.
There are also studies that have used FPGA and DWT for image compression using distributed arithmetic which includes increasing number of shift registers on LUT.The techniques using DWT and FPGA cannot optimize the entropy encoding.
 Less Emphasis on Vedic Multipliers: There are only 2 transaction papers and 155 conference papers on Vedic-based approaches published during 2010-2016 in IEEE Xplore.However, about radiological image compression, there exist only two conference papers that have implemented Vedic multiplier during last 5 years [36][37].This itself is one of the potential evidence that there has been quite a less emphasis on standard research work towards realizing the potential characteristics of Vedic-based approaches in medical image compression.
Apart from the above-mentioned problems, it was also found that existing techniques suffers from certain common problem viz.i) lack of benchmarking, ii) inappropriate architecture usage leading to poor process of image reconstruction, ii) considers the entire image for compression leading to more bandwidth utilization as well as computational resource utilization, etc.Moreover, the potential of the Vedic multiplier, DWT and FPGA are less explored jointly.Hence, the problem statement can be stated as -It is a challenging task to develop a faster radiological image compression considering the joint potential of DWT, FPGA, and Vedic Multipliers.‖The next section about the methodology adopted in to address the identified problems.

IV. PROPOSED METHODOLOGY
The design and implementation of the proposed work are carried out using analytical-based methodology.The present work is a continuation of our prior works [36][38] [39].The proposed system implements Vedic multiplier called as Urdhva-Tiryagbhyam.The beneficial point of this multiplier is that it can concurrently handle addition and fractional product generation.This feature gives more edge to parallel processing that can significantly reduce the delay time.It also makes it highly suitable for performing binary multiplication.Fig. 1 highlights the architecture designed for the proposed system.The proposed system uses Region-of-Interest for taking the input of radiological image, which means the proposed algorithm is only applicable to ROI and not the complete radiological image.It than converts the image into a binary text file, so that it can be processed effectively in FPGA.The next step is to apply lifting scheme which has its inherent advantages over eliminating redundancies.It works by classifying the ROI data to even and odd samples further followed by prediction and updating operation.Prediction process assists in obtaining approximated coefficients while updating operation assists in obtaining detailed coefficient values.This step is carried out to resist lossy data and to obtained lossless data during the entire process of radiological image compression.Finally, it generates high and loss pass components of one-dimensional DWT which is further processed back to obtain two-dimensional DWT in the form of a reconstructed image.The elaborated discussion of the algorithm of proposed system is carried out in next section.

V. ALGORITHM IMPLEMENTATION
The main purpose of this algorithm is to perform radiological image compression using the Vedic multiplier.The proposed system uses radiological image database of [40] in algorithm implementation.In spite of compressing the entire image, we choose to compress only the Region-of-Interest (ROI).The advantage is faster processing, less allocation of computational resources, and retention of the image portion of clinical importance.The proposed system uses Matlab to take the input of radiological image and then convert it into a text www.ijacsa.thesai.orgfile (a form of a hexadecimal number), which is further subjected to FPGA (Line-2).The entire algorithm implementation is carried out over FPGA itself.It is already known that a filtering operation can be carried out over DWT that can be represented as, In the above equation, TL(i) and TL(i) corresponds to transfer function of low as well as high pass filter.It also means that TL e (i) and TH e (i) corresponds to even components while TL o (i) and TH o (i) represents odd components.The better representation of the transform function could be, (2) In the above equation, the variables φ(i) and θ(i) represents both low and high pass components that have been filtered from its input signal x(i).The proposed system also uses lifting scheme that can further factorize the matrix representation giving better feasibility to enhancing the capability of the processor.Another advantage of applying lifting scheme will be to eliminate the redundancies.As per Fig. 2, even clocking will be functional on the registers position on top while odd clocking will be operational for the registers positioned on the bottom.Using a clock cycle of a unit pixel, the ROI image data is fed in serial order to classify the data as even (c e ) and odd components (c o ) (Line-3).This operation will lead to the implementation of lifting scheme that further results in low pass components (LP c ) and high pass components (HP c ) (Line-4).A unit of low pass coefficient, as well as high pass coefficient will be generated for a single unit of ROI image.

End
The generated low pass component and high pass components are then identified.The proposed system also makes use of Daubechies 9/7 filters.The advantage will be an enhancement in the compression performance will be retained to maximum level with proper control over computational complexity.This implementation policy can be seen in Fig. 1, where the ROI image data is forwarded through numerous steps.The numbers of transformed coefficients are retained to be similar as that of original one owing to sub-sampling.The system than processes the data to obtain detailed (x 5 (i)) and approximation coefficients (x 6 (i)) of one-dimensional DWT (Line-5).Implemented over FPGA using Verilog, the coefficient outcome was obtained.The next part of the algorithm implementation is to apply Vedic multiplier design using hardware-based architectural approach (Line-6).The implemented design scheme of the Vedic multiplier was shown in Fig. 3. www.ijacsa.thesai.orgThe proposed technique has been testified for both 2x2 as well as a 4x4 bit of Vedic multiplier to design the hardware architecture.The system uses Urdhva Tiryagbhyam sutra which is meant for vertical and crosswise multiplication of dual-number of binary origin.Initially a 4x4 bit of Vedic multiplier has been designed, which further uses 8 bit of ripple carry added to formulate an 8x8 bit of Vedic multiplier.The entire process starts with 2 bit numbers say P and Q to for 2x2 bit of Vedic multiplier using vertical and crosswise multiplication of least significant bits.It is then enhanced with 4x4 bit of Vedic multiplier considering two-bit at a time in 2bit block of the multiplier.Although, it can reduce delay, the delay performance can be further enhanced by considering four 4x4 bit of Vedic multiplier and three 8 bit of ripple carry adder.Consider P=P 7 P 6 P 5 P 4 P 3 P 2 P 1 P 0 and Q=Q

Splitter
Therefore, according to the concept of Vedic-based multiplication, it will result in 16 bits as T 15 T 14 T 13 T 12 T 11 T 10 T 9 T 8 T 7 T 6 T 5 T 4 T 3 T 2 T 1 T 0 .Dividing the bits P and Q will result in further decomposition into a pair of minimum 4 bits of sub-bits e.g.P high and P low .Similar generation will be yield by Q also as Q high and Q low.The further processing of multiplication is carried out by utilizing 4 bits of multiplier blocks and considering 4 bits at a single instance, which is by the Vedic multiplier theorem of Urdhva Tiryagbhyam sutra.Finally, the resultant is accomplished from the addition of the multipliers of 4x4 bit output.In this entire process, three ripple carrier adders of 8 bits are also used as shown in Fig. 3.The final-outcome from the FPGA is than fed to Matlab to obtain a reconstructed image (Line-7).Hence, the proposed system wisely utilizes the Vedic multiplier to enhance the compression performance over radiological images.The next section discusses the results being accomplished by the implementation of the algorithm discussed in this section.

VI. RESULT DISCUSSION
The proposed system was implemented on 32 bit windows system with normal 4 GB of RAM and core-i5 processor.The implementation is carried out over two types of FPGA devices i.e. i) Virtex 4 FX100 -12 FF1152 and ii) Spartan 3 XC400-5TQ144.The formation of the one-dimensional DWT with Vedic multiplier using Xilinx and Verilog is shown in Fig. 4 Fig. 4. Module of 1D_DWT Upon receiving the input data, it is classified in even and odd components which are then reposited in registers.The registers will have a null value when there is higher reset, but during lower reset, the registers classify the input ROI image in the form of odd and even components.The lifting schemes enable to read the input ROI data to 16 clock cycles whereas the resultant outcome will have both high and low pass components according to the algorithm steps (onedimensional-DWT).The module shown in Fig. 4 takes the input of pixel values, which categorizes the values in odd and even components and develops a matrix where it is stored.This operation is then followed by the Vedic multiplier to further leverage the compression process.Fig. 5-6 shows the visual outcomes of the two sample radiological image whose ROI is considered for performing compression operation using proposed system.Both the visual outcomes show accomplishment of one-dimensional DWT outcomes, which is then followed by two-dimensional DWT outcomes.A closer look at the reconstructed two-dimensional DWT image shows better perceptibility of the processed radiological image after applying compression.www.ijacsa.thesai.orgThe work carried out by Todkar [41] was mainly focused on enhancing the operation of two dimensional DWT over VLSI-based architecture.The authors have used 9/7 filter design as the lifting scheme that is quite similar to us.The technique has minimized the higher dependencies of registers to have better control over a delay.The authors have amended the design of DWT, transpose unit, processing elements, and mechanism of prediction and update.The implementation was carried out using 16 multipliers, 5 input buffers, 54 registers, 24 adders, and 11 transposition registers with lifting based DWT scheme.The numerical outcome was presented in Table 1 using FPGA device (Virtex 4 FX100 -12 FF1152).The first significant improvement can be seen is the lowered dependencies on the utilization of slices by proposed system and it almost doesn't use any flip flops.The complete processing time of the algorithm for proposed system is found to be 47% improved as compared to Todkar's approach [41] with less computational complexity The above Table 2 shows the numerical analysis of proposed system with that of work carried out by Mhamunkar [42].The author have used frequently used image compression algorithm i.e.SPIHT with an objective to maintain balance between compression and image quality over FPGA.The algorithm processes the input image in order to extract the header files and deployed hardware customer logic and used micro blaze processor over FPGA to perform SPIHT encoding and decoding.We have maintained the similar environment of implementation by considering the equivalent FPGA device (Spartan 3 XC400-5TQ144).The result shows that there is a considerable amount of improvement in all the performance parameters of proposed system in contrast to the recent work carried out by Mhamunkar [42].
The proposed system takes the odd and even components after it explores the high signal load in order to deploy it for generating low pass coefficients.This operation is exponentially speeded up by using enhanced Vedic multiplier, which has the further capability to minimize area as well as delay as compared to any traditional mechanism of radiological image compression.During the entire observation, it was found that proposed system has significantly lowered the dependencies on full adder as well as a half adder in comparison to usage of ripple carry adder.Implementation of DWT-based approach has further ensured retention of the maximum degree of signal quality of the reconstructed image.www.ijacsa.thesai.org

VII. CONCLUSION
This research paper has presented an idea of performing compression of radiological images.Even after decades of research work towards image compression, this field has not witnessed a robust compression algorithm yet.In spite of availability of various compression schemes, the applicability of them in medical images are quite less owing to its dependencies on lossless compression scheme.After reviewing literature, it was explored that usage of DWT along with lifting schemes and FPGA are good possibilities to accomplish such lossless data during compression.Further, it was also found that potential characteristics of Vedic multipliers towards addressing the problems in compression are also left untapped in existing research work.Hence, a novel techniques have been discussed that jointly utilizes DWT, FPGA, and Vedic multiplier to accomplish an objective of cost-effective medical image compression.Our outcomes are also compared with similar kinds of schemes being recently published to find that proposed system exhibits a better balance between compression and image quality.

Fig. 7 .
Fig. 7. Simulation results of 2D-DWT Fig.7 highlights the simulation outcome of two dimensional DWT in FPGA.For effective analysis, the design of the proposed system is compared with the similar type of work presented by Todkar [41] and Mhamunkar [42] most recently.The standard performance parameters are retained e.g.logic utilization, number of slices, number of slice flip flops, number of 4 unit LUT, and number of bonded IOBs.