Design of 1-bit Comparator using 2 Dot 1 Electron Quantum-Dot Cellular Automata

In nanotechnologies, quantum-dot cellular automata (QCA) offer promising and attractive features for nano-scale computing. QCA effectively overcomes the scaling shortfalls of CMOS technology. One of the variants of QCA is 4 Dot 2 Electron QCA which is well explored and researched. The main concentration of this study is on 2 Dot 1 Electron QCA, an emerging variant of QCA. A novel and efficient XOR gate based on 2 Dot 1 Electron QCA is designed. Moreover a comparator using the proposed novel XOR gate is presented in this present scope. The proposed architecture is justified using a wellaccepted standard mathematical function based on Coulomb’s law. Energy and power dissipation of the architecture are analyzed using different energy parameters. AS the compactness of proposed design is 76.4% the design met high degree of compactness and better efficiency. Keywords—QCA; 2 Dot 1 Electron QCA; Comparator; Coulomb’s principle


INTRODUCTION
Expansion of cost-effective, efficient nanotechnologies is conducting owing to obtain the performance that is not attainable by CMOS technology due to its scaling limits like off-state leakage current, degrading switching activity, etc. Quantum-dot cellular automata (QCA) technology is one of the up-and-coming replacements to overcome the scaling limits of CMOS [1]- [3].QCA provides efficient properties including high-speed nano-scale designs at terahertz frequency range, long lifetime small feature size, together with low power consumption, ultra-low power dissipation [4]- [6].
One of the recent variant of QCA is 2 Dot 1 Electron QCA which offer all the advantages of QCA technology over conventional CMOS technology together with benefits over the 4 Dot 2 Electron QCA structure.The most advantageous aspect of 2 Dot 1 Electron QCA over 4 Dot 2 Electron QCA is the total number electron in the cell is halved, so energy requirement is reduced.There exits four ambiguous configurations in 4 Dot 2 Electron QCA, only two of them are valid.However, there is no ambiguous configuration in case of 2 Dot 1 Electron QCA [7]- [9].Moreover in 2 Dot 1 Electron QCA wiring complexity is minimized as binary information can be transmitted from one cell to another using cell-to-cell interaction and obeying Coulomb"s repulsion principle.
Comparator is fundamental digital devices and essential component for modern computing environments.There are diverse form of existing literature on comparator design using 4 Dot 2 Electron QCA as in [10]- [15].Comparator design using 2 Dot 1 Electron QCA is unexplored till now.This article proposes an optimized comparator implemented using 2 Dot 1 Electron QCA cell.
The later part of the study is structured in the following way.Section II represents the overview of 2 Dot 1 Electron QCA.Section III offers design and scheme of a novel XOR gate.The design of proposed 1 bit comparators using the novel XOR gate is presented in section IV.Section V verifies the output energy states using standard mathematical procedure.Effective area analysis of the proposed architecture is provided in section VI.In section VII energy and power dissipation to run the proposed design is briefly analyzed.Finally Conclusion is demonstrated in section VIII.

II.
OVERVIEW OF 2 DOT 1 ELECTRON QCA The building block of Quantum dot Cellular Automata are cells and quantum dots or holes.Different formations of cells lead to different variants of QCA.Two dimensional 2 Dot 1 Electron QCA is the structural variation of QCA.As the name clearly suggests that a 2-Dot 1-Electron QCA cell consists of two logically interacting quantum dots and one electron.Single electron can move between the two quantum dots through the tunnel.Also, the single electron in the cell is able to represent binary information by the occupancy of electron in the quantum dots.
The cell structure of 2 Dot 1 Electron QCA is rectangular, either vertically or horizontally oriented along with two dots are at the two ends [9].The structure of the 2-dot 1-electron QCA cells and their polarities are shown in Fig. 1(a) and 1(b).The position of the electron within a cell represents binary information.
In case of vertical cell when the electron positioned in the quantum dot below, and above, represent binary "0" and "1" respectively shown in Fig. 1(a) and 1(b).In the same way, in horizontal cell when the electron positioned in the right and left quantum dot represent binary "0" and "1" respectively.However, like 4 Dot 2 Electron QCA 2 Dot 1 Electron QCA has fundamental design constructs such as binary wire, inverter by oppositely positioned cell between two same oriented cell of a binary wire, planar crossing of wires [7], www.ijacsa.thesai.orginverter by placing cell at corner and majority voter gate as depicted in Fig. 1 (c), 1 (d), 1(e), 1(f) and 2 respectively.

A. QCA Clocking
In CMOS technology clocking is used for the purpose of synchronization, whereas; in 2 Dot 1 Electron QCA architecture clocking fulfill two purposes.One is to control direction of data flow and other is to empower the weak input signals since they can traverse the whole circuit [8].QCA clocking consists of four phases namely switch, hold, release, and relax.
One clock zone is out of phase with the subsequent clock zone by π/2 as depicted in Fig. 3(a) and several color codes indicate various clock zone as shown in Fig. 3(b).
In switch phase, initially electrons into the quantum dots contain minimum energy.The input signals are not adequate enough to empower the electrons.After that clock signal amplitude increases and potential energy of electrons begin to rise.Finally electron gains highest potential energy at the end of this phase.During the hold phase, the high phase, electrons become effectively energized to exceed the tunneling barrier.At this phase electrons loose polarity and get completely delocalized.The cells are stated to obtain null phase.
In the release phase, the high to low phase, actual computation is performed and electrons start to dissipate potential energy.They latch at the other quantum dots.The cells gradually begin to obtain a certain polarity.
In the relax phase, the low phase, electrons bear minimum energy and confined into the quantum dots.The cells in one clock zone will perform as input for the next clock zone.

III. THE NOVEL EX-OR GATE
A several form of XOR (exclusive-OR) gate has been designed until now [16], [17] and most of the cases utilized 3input majority gate.In digital logic circuit designs XOR gate is an exigent element.Different XOR-based circuits have been designed yet, owing to the great essentiality of XOR gate [18].Fig. 4 illustrates the 2 Dot 1 Electron two input XOR Gate.However, the novel 2 Dot 1 Electron two input XOR Gate is not majority based rather it utilizes explicit interactions among QCA cells to determine the expected output.www.ijacsa.thesai.orgIV.
PROPOSED DESIGN OF 1 BIT COMPARATOR 1 bit comparator as the name indicates that this digital logic circuit could be utilized to compare whether two 1 bit binary numbers are identical.Moreover it also identifies which number is larger.Therefore in logic circuits design 1 bit comparators are used for decision making.Fig. 5 illustrates the schematic of 1-Bit Comparator using logic gates.[9], [20].
The calculation of potential energy between two electron charges is done using the following equations.

  ∑
 Where U indicates the potential energy between the two electron charges q1 and q2, K is the Boltzman constant and r denotes the distance between the two point electric charges.U T denotes the total potential energy for a specific electron position because of the effects of all of its neighbor electrons.Electron and quantum dot contains negative charge and induced positive charge respectively.Electron, due to its characteristics always tends to reach at a position with least potential energy.Thus, to evaluate the output state of the proposed design, comparative analysis of the total potential energy is calculated for each of the allowable electron positions within a cell.Let, each of 2 Dot 1 Electron QCA cell has length = 13 nm and the space between two cell = 5 nm.Fig. 6 represents the numbering of cell of the proposed comparator design using 2 Dot 1 electrons QCA and Table II presents respective potential energy evaluations.

VI. EFFECTIVE AREA ANALYSIS
As mention before the structure of 2 Dot 1 electron QCA cells are rectangular.Consider the length and breadth of a 2 Dot 1 electron QCA cell is p and q respectively.Therefore area www.ijacsa.thesai.org of each cell is p×q nm 2 .To form the proposed 1 bit Comparator 55 number of 2 Dot 1 electron QCA cell is required as shown in Fig. 6 Thus the effective area under the architecture is 55pq and the area covered by the architecture is 72pq.The ratio of area utilization of the proposed architecture is 55:72.The compactness is 76.4%.Hence the design met high degree of compactness.

VII.
ENERGY AND POWER DISSIPATION ANALYSIS Various expressions are used as in [22], [23] to calculate energy parameters.E m is the minimum energy to be provided to the scheme with N cells; E clock is the energy applied by the clock to the circuit with N cells; E diss is dissipation of energy from the circuit with N cells;  2 denotes frequency of energy dissipation; τ 2 is the time to dissipate to arrive to the relaxed state into the environment;  1 is the frequency of incident energy; τ 1 is the time needed to arrive from quantum level n 2 to the quantum level n. τ is the required time by the cells to switch from one to the subsequence polarization in a particular clock zone; t p is propagation time to the entire circuit;  1 - 2 indicates differential frequency.All of these parameter values for proposed 1 bit comparator are determined in Table III.

-40
Gain same polarity of input cell B.

-15
Gain same polarity of input cell A.

VIII. CONCLUSION
This present scope proposes an improved design methodology of 1 bit comparator using 2 Dot 1 Electron QCA which attains high degree of compactness and require lesser amount of energy to run.Since there is no open source simulation tool existing for 2 Dot 1 Electron.Therefore, potential energy calculation is applied in order to justify the proposed design.In addition effective area and stability is presented to analyze the acceptance level of the architecture.Several energy parameters and power dissipation are also analyzed for the proposed scheme.

TABLE .
III. SEVERAL ENERGY PARAMETER VALUES FOR PROPOSED 1 BIT COMPARATOR