Mobility based Net Ordering for Simultaneous Escape Routing

With the advancement in electronics technology, number of pins under the ball grid array (BGA) are increasing on reduced size components. In small size components, a challenging task is to solve the escape routing problem where BGA pins escape towards the component boundary. It is often desirable to perform ordered simultaneous escape routing (SER) to facilitate area routing and produce elegant Printed Circuit Board (PCB) design. Some heuristic techniques help in finding the PCB routing solution for SER but for larger problems these are time consuming and produce sub-optimal results. This work propose solution which divides the problem into two parts. First, a novel net ordering algorithm for SER using network theoretic approach and then linear optimization model for single component ordered escape routing has been proposed. The model routes maximum possible nets between two components of the PCB by considering the design rules based on the given net ordering. Comparative analysis shows that the proposed net ordering algorithm and optimization model performs better than the existing routing algorithms for SER in terms of number of nets routed. Also the running time using proposed algorithm reduces to O(2) +O(2) for ordered escape routing of both components. This time is much lesser than O(2) due to exponential reduction. Keywords—Net ordering; optimization model; ordered escape routing; PCB routing; simultaneous escape routing


I. INTRODUCTION
With the advancement in technology, the demand for small size electronic components with larger number of pins increases [1].These components can be Integrated Circuits (ICs) or BGA type with hundreds of connectivity pins [2]- [4] in the form of grid.Usage of such components necessitates sophisticated design and advanced technologies for producing small sized electronic circuit boards.Multiple BGAs need to be connected on the PCB, which require connectivity of pins by routing of nets.This kind of routing has two parts, one is escape routing which is from pin to the boundary of the component and the other is area routing which is between the components as shown in Fig. 1.Presence of BGA components on smaller sized PCBs significantly increases the routing complexity.
Routing in PCBs is the problem of connecting the pins of different components on the PCB to make it operational.The circuit wire lying on the PCB, between the pins pair (that needs to be connected) is called a net.Routing of nets becomes more complex, if there are more number of nets and needs ordered escape routing.Ideally, the routing algorithm shall connect all nets as a planar graph (nets don't cross each other) and the nets shall be entirely contained within the area of the PCB.Given the high density of components on smaller sizes PCBs, and hundreds of nets to route.A single layer is not enough to route all nets in a planar fashion particularly if ordered escaping is required.Therefore, multiple routing layers are used to ensure planarity as shown in Fig. 1.PCB routing for given set of connectivity pins is similar problem as constructing of planar graph for a given set of nodes, which is known to be NP-Hard [5].BGA components have small size balls/pins under the surface, in the form of a grid.This high density grid reduces the net escaping space and make the routing more complex.Therefore, PCB routing is divided into two parts: 1) escape routing where routing is to be done from pin to the component boundary; and 2) area routing where the net between one component to other component is established as shown in Fig. 1.To facilitate the area routing, escape routing is required in some particular order.Therefore ordered escape routing is a major challenge in PCB routing, which becomes even more challenging for simultaneous escape routing (SER) [6]- [12].In SER pin escaping for multiple components is done simultaneously in a specific order to reduce the complexity of area routing as shown in Fig. 2. To reduce the complexity of SER, the problem has been divided into two parts i.e. ordered escape routing of two components separately.In this case, net order has necessarily required.
Focus of this research is to find the net order for simultaneous escape routing.In this paper, an algorithm to find the net order has been proposed.This reduces the problem into half and reduces the complexity of routing by many times.In this way the area routing becomes very simple and it is just a www.ijacsa.thesai.org• In the first step an algorithm to find the optimal net order has been proposed.This algorithm helps by converting the complex problem of simultaneous escape routing into simple and single component ordered escape problem.Ultimately this exponentially reduces the complexity of the problem.
• In the second step ILP optimization model for ordered escape routing has been modified, which helps in finding the ordered net escape from a single component.
Collectively these two contributions help in solving SER problem in a much better way.
The rest of the paper is organized as follows: In Section 2, some basic techniques used for planar routing and advancements in this area with a review of the latest literature has been discussed.Section 3 presents proposed algorithm to find a net order.In Section 4, optimization model for ordered escape routing under the constraints of planar routing and escape capacity has been proposed.In Section 5, algorithm/model val-idation and comparative evaluation of the proposed algorithm has been performed.Section VI concludes this work.

II. RELATED WORK
Routing of nets on PCB, is divided into two main categories, one is area and the other is escape routing [7].The objective of escape routing is to establish the planar routes by escaping the nets from pins to the component boundary in an ordered or unordered way, based on constraints on available capacity between adjacent pins.With the escape routes established, the problem of PCB routing is reduced to conventional PCB routing problem of area routing [13], [14].
Escape routing is of three types [15]: 1) Unordered escape routing where there is no particular sequence of pin escaping towards component boundary from a single component [15]- [21]; 2) ordered escape routing where there is a particular sequence (order) of pin escaping towards component boundary from a single component [22] (one of the example of this type of routing is Bus escape which is also called as maximum disjoint subset problem [23]); and 3) simultaneous escape routing where pins from multiple components escaped in the same order.This problem relatively more complex as compare to other escaping problems.To find the solution of SER is time consuming process, particularly for larger problems.This time can be reduced if the escape net order is known in advance.Escape net order is a sequence of nets to escape from the boundary of a component.This prior net ordering information converts the problem of SER into ordered escape routing of a single component.Focus of this work is to find the optimal net order.The following subsections discuss the related literature in detail.

A. Simultaneous Escape Routing
The initial research work proposed for SER consists of two parts.Unordered escaping of pins proposed in the first component whereas for the second component, ordered escape routing proposed to match the pins of first component to get SER solution.However, this approach might results in an incomplete routing.Ozdal et al. [7] carried out the first well known SER research.Graph based approach was used to find maximal escape nets.This approach gives better results only if the pins of both components are closely aligned to each other.However, complex problems of SER cannot be solved using fixed escape patterns used in this approach.Ozdal et al. [8] also proposed randomized algorithm for large scale problems in their extended work.However, proposed monotonic escape of nets in one direction cannot produce optimal results and also it limits its applications.For routing pattern generation, Ozdal et al. [9] also used congestion driven router, however for large scale SER problems the graph of escape patterns becomes complicated.Simultaneous Pin Escape [12] is a flow model based approach.Authors show that for a particular probelm if construction of planar graph is possible then this approach guarantees planar routing.The existence of a solution can be determined by the relation between maximum flow and number of escape pins of the BGA component [12], [16].This approach must provide a planar solution if maximum flow is greater or equal to the escape pins; however, for higher inter pin capacities 'no net crossing' cannot be ensured and exact value of maximal flow is not known.A bus oriented escape routing with consecutive constraints has been proposed for SER on multiple layers [24].The focus of this research is to reduce the CPU time, however if the pins are randomly placed on each component then its very difficult to form buses and also unable to get optimal routing solution due to escaping of nets in the form of buses.

B. Net Ordering Algorithms
B-Escape is a routing algorithm proposed by Luo et al. [10].This algorithm uses dynamic net ordering approach and performs well when compared with Allegro PCB router [10]; however it consumes significant time to find a suitable net order and in reordering of nets again and again.Rout-ability Driven Net Order proposed by Yan et al. [25] is a multi-step approach.An important step is identification of a net ordering, which is derived on the basis of planar bipartite graph theory.A subsequent step uses global and detailed routing technique under the constraints of planar routing and escape capacity.This approach improves the computation time by 54.1% as compared to Kong et al. [12].The drawback is that the second step is totally dependent on the output of the first step i.e.net ordering.It does not explore all possible paths and may lead to sub-optimal results in complex problem instances.
Escaped Boundary Pins Routing for High-Speed Boards proposed by Chin et al. [26] is an algorithm for finding static net ordering by dynamic pin sequence (DPS).Another work proposed by Kumtong et al. [27] is based on set sequence (SS) technique.While these algorithms can better utilize the routing space and adapt to wire length and shape requirements, their focus is on boundary pin routing and are not suitable for BGA type of PCB components which need escaping from inside the components; their use can also be more challenging, particularly in case of SER.
Most of the research on SER is based on basic constraints of capacity and construction of planar graph.Also most of them are using heuristic approaches to get the routing solution.This research considers optimization theoretic approach.Instead of solving the problem in parts to get sub-optimal solution, this optimization approach is expected to produce optimal results.This approach not only considers capacity and planarity but also considers constraint of power-signal integrity, net route length and net escape order altogether, to solve the SER problem at the cost of higher computational time.However, with high speed computing units, clustering of computational resources to perform complex computational tasks and using net ordering techniques, the drawback can easily be overcome.In this research an algorithm for optimal net ordering has been proposed which reduces the computational time and outperforms the existing algorithms.

III. ALGORITHM FOR NET ORDERING
This section, first define the terms used in the algorithm and then discuss the tile model and net ordering algorithm in detail.It is also assumed that there are only two components and only one side escape is possible from the side of component, which is facing towards the other component.
Rows Ci : Number of rows of pins for component Ci.
Orthogonal Cap : This capacity refers to the number of nets that can pass through between two neighboring pins vertically or horizontally.
Diagonal Cap : It refers to the number of nets that can pass through between two neighboring diagonal pins.
Cap Ci : Escape routing capacity for component Ci.

A. Net Ordering Algorithm
This proposed algorithm performs four basic functions in sequence as discussed in Algorithm 1, which are SER Capacity(), Initial N etOrder(), U RDF M obility V alues() and F inal N etOrder() respectively.This algorithm produces the optimal net order for SER, if it exists.Then escape routing for each component performed separately according to that net order with the help of an optimization model.
Routable ⇐ SER Capacity() print 'Complete Routing not possible' and exit 13: 1) SER Capacity Function: SER Capacity() function has been discussed in Algorithm 2. First calculate the escape capacity of each component.Here BoundaryP ins Ci has been added in Cap Ci , because they can escape directly from the component boundary without effecting the other nets or orthogonal capacity.Obviously the SER capacity must be the minimum escape capacity of both components.Then it is also verified whether the routing with the required number of nets n is possible or not.
Consider an example instance of two BGA components of size 6x4, having 5 connectivity pins as shown in Fig. 3. Also consider left component as C1 and right component as C2.Rows C1 and Rows C2 are 6, whereas Orthogonal Cap is 1.Since there is no boundary connectivity pin, therefore Cap C1 is 5 and Cap C2 is also 5.According to Algorithm 2, SER Cap is also 5.There are 5 pins which need connectivity (escape routing) and these are less than or equal to the SER Cap , therefore the Algorithm 2 returns true and move on the next step of the main Algorithm 1.   2) Initial Net Order: To find the initial net order according to the position of pins in the grid of the component, Initial N etOrder() function in Algorithm 3 has been discussed.Also some rules for rearrangement of the initial net order has been defined.
In the first step, convert each row in a vertex for both components as shown in Fig. 4. Then for the rows having multiple connectivity pins apply the rules defined in Step 2 to Step 13 of Algorithm 3. In this example there is Pin-3 on nonescape boundary of left component and also there is one pin above that row whereas there are two escape boundary points above that row.Therefore select Pin-3, first in order.Similarly select Pin-1, first in order in the right component.In the third step connect all pins to their corresponding pins with edges, as shown in Fig. 4. Read row wise all pins from top to bottom and put them in column form, separately for each component.order must be from the escape side to nonescape side.

6:
else if there are multiple pins in a last row then 7: order must be from the non-escape side to the escape side.select from the escape side to the non-escape side. 12: For all other rows order should be according to the row number of the corresponding pin in the other component.

4) Final Net Order:
The last function of Algorithm 1finds the final net order as shown in Fig. 6, by eliminating a crossing of edges among two columns.To eliminate the cross, there are four possibilities.For example, consider the first crossing between Pin-1 and Pin-5, as shown in Fig. 5.The first possibility is to move the Pin-5 in left column to the top of the Pin-1 in the left column.Second possibility is to move Pin-1 in the left column to the bottom of the Pin-5 in the same column.Similarly, the third possibility is to move the Pin-1 in the right column to the top of Pin-5 of the right column and finally the fourth possibility is to move Pin-5 of the right column to the bottom of Pin-1 in the same column.Try all the four possibilities in some order, till selection of one, which is allowed by U RDF values as discussed in Algorithm 5. Failure of all the possibilities shows that routing of both nets is not possible in this scenario.
In final net ordering process, initially considers first pin of each column, which is Pin-1 and Pin-5 as shown in Fig. 6.Since the row of Pin-5 in its component is higher (smaller row number), therefore select Pin-5 and try to move its corresponding pin from left component towards upside.But on the way there is Pin-3, which has rear value, R = 0.This implies that Pin-5 cannot route from rear side of Pin-3.Therefore, first move Pin-3 towards downside of Pin-5.Since the rear and down values of Pin-5 are greater than zero, hence route Pin-3 from the rear side of Pin-5.After the routing of Pin-3, route Pin-5 towards upside at the level of selected Pin-5 of right component as shown in Fig. 6.In this way eliminate all the crossings and get the final nets order if exists.The proposed algorithm not only converts the SER problem into much simplified ordered escape routing problem by providing the net order, but also provides the global routing of each net.In the next section optimization model for detailed routing is being used.

IV. OPTIMIZATION MODEL FOR ORDERED ESCAPE
Optimization models are very helpful to solve real life problems [28], [29].These models provide optimal solution by considering all constraints.This section presents the modified Integer linear program based optimization model proposed in Consider a current variable, which initially points to the first pin of each column.In each iteration, the current variable moves to the next row.Let Pin-A be from left column and Pin-B be from the right column.

3:
Select the pin according to the following rules: select it first and arrange its counter pin.select that pin first.If, by this choice, any pin is being blocked then reselect that pin first.select the pin whose row number is lesser.

14:
Route the selected pin (e.g A) by moving its counter Pin-A' (or both in case C is selected) towards upside in a column to reach at current row level by these rules: 15: if First pin to move upward then 16: move the counter Pin-A' (both in case of C) upward from the rear side of all the pins, till reaching at current row level to eliminate the edge crossing.17: else if on the way any pin have R=0 or U=0 then 18: first move that pin below the counter pin A' (counter pin must have R>0 and D>0).If there is more than 1 pin which faces this situation then order of moving down pins is from escape side to non-escape side.update the mobility values.The value in each direction will be either the distance between the pin and the net passing through in that direction or connected pin whichever is lesser.Move the current variable to the next row and goto Step 3.

25:
if eliminate all crossings by reordering pins then 26: this is our final net order and the function returns true.our earlier work [30].System constraints from the model has been removed because these are useless once net order has been finalized.The graph G(V, E) serves as input to this model, where V is a set of vertices.This set consists of boundary points, intermediate points and connecting pins.All the possible edges are in set E and the nets use these edges for escape towards the boundary of the component.
Based on the given constraints, the proposed model returns another graph G (V , E ) , which shows the maximum number of possible escaped nets, with G (V , E ) ≤ G(V, E), which also implies that V ≤ V and E ≤ E. Linear programming model has been formulated that can perform escape routing of nets from a component according to the given net order identified in the previous section.These are the sets used as input in the proposed model: N = Set of required nets.I = All intermediate and boundary points.V = All intermediate points, boundary points and connecting pins.BE= All edges at the component's boundary.E = All possible edges of a BGA.The proposed model contains decision variable X (na,eij ) , which is a Boolean variable for all nets n a ∈ N and for all edges e ij ∈ E. If the solver assign true or 1 to the decision variable then that edge e ij for a particular net n a for escape routing is being used, otherwise the solver assigns false or zero value to the decision variable.
1 if e ij edge is being used for net n a 0 if e ij is not being used for n a By using this optimization model, routing is constrained by the constraints of connectivity, planar graph, net order and system constraint.Each constraint is important in terms of achieving error free routing designs [30].The following set of equations ( 1)-( 6), completely represents the optimization model.

max .
na∈N eaj ∈E X (na,eaj ) (1) subject to: X (na,e jk ) ∀n a ∈ N, ∀j ∈ I (3) V. EVALUATION Proposed net ordering algorithm has been implemented in C++ and for detailed routing, optimization model has been implemented in AMPL language [31].Initially, the proposed algorithm and optimization model has been validated in Subsection V-A and V-B, respectively.Subsequently the performance is being evaluated in Sub-section V-C.

A. Algorithm Validation
This section verify that the algorithm proposed in Section III, gives the optimal net order if SER has a valid routing solution.Furthermore if a particular scenario has no complete routable solution then it return false.Algorithm validated for this purpose on BGA component as shown in Fig. 3.Both components C1 and C2 have 6 rows from A to F and 4 columns from 1 to 4. There are 5 connectivity pins in each component that needs escape routing to connect with each other.To simplify the explanation, in this example assume Orthogonal Cap = 1 and Diagonal Cap = 2. Twelve (12) scenarios has been considered with randomly selected 5 escape pins in each component.In the first scenario, first pin is at location B4 in C1 and location E2 in C2.Similarly see the location of other pins in Fig. 7.The net order obtained by our proposed algorithm is 1,3,2,4 and 5. Then run the same scenario in commercially available Proteus auto router by Labcenter Electronics Ltd.The result obtained by Proteus is exactly in the same order as obtained by our algorithm as shown in Fig. 7.
Complete validation results can be seen in Table I.First column is the scenario number, second and third columns are the pin positions in each component respectively from Pin-1 to 5. Fourth column is the net order obtained by the C++ program for the proposed algorithm and the fifth column is the net order obtained by the Proteus router.Results validate the algorithm for all scenarios.In some cases the algorithm returns false, which implies that complete routing for all the nets is not possible as shown in Scenario 7 of Table I.Running the same scenario in Proteus, resulted in the un-routable solution as shown in Fig. 8. Routing of Pin-1 from B3 of component 1 to F2 of component 2 is not possible, which validates the results.

B. Model Validation
Consider Scenario 1 of Table I for the validation of model.The net order obtained by the proposed algorithm is 1, 3, 2, 4, and 5.This net order converts the SER problem into two single components ordered escape routing problems.This example clearly shows that the optimization model efficiently performs ordered escape routing for PCB components based on BGA, as shown in Fig. 9.There are maximum 5 boundary points in the BGA component and model chooses to route all five nets by escaping in a given order.It is evident that this solution ensures planarity by not selecting any vertex or edge twice.The routing of nets is exactly the same as obtained by Proteus auto router as shown in Fig. 7.This example performs comprehensive validation of proposed optimization model and ensures all constraints of connectivity, net order and planar graph.

C. Performance Analysis
The performance comparison in this section is to find the optimal net order by comparing the results of our proposed mobility based net ordering (MBNO) algorithm with the routability driven net ordering (RDNO) algorithm [25].Consider three different scenarios of the same examples discussed in [25] for the purpose of evaluation.In this example there are 9 rows and 10 columns for both components, having 90 pins in total.There are 14 nets, which need connectivity and escaping of pins for SER.Also single side escape is permitted with Orthogonal Cap equal to 2 and the Diagonal Cap equal to 3. Each scenario highlights different aspect of the proposed  algorithm as explained in respective sub-section.
1) BGA 9x10 Default case Scenario-1: To validate, results obtained by our proposed MBNO algorithm has been compared with the results obtained by RDNO algorithm.For the default example discussed in [25] both provided the optimal net order.Fig. 10 shows the output of RDNO algorithm and the net order is: 14, 6, 2, 5, 3, 10, 11, 4, 1, 9, 7, 8, 12, 13.Whereas Fig. 11 shows the output of the proposed algorithm and the net order is: 14, 6, 2, 5, 3, 10, 4, 11, 12, 9, 1, 13, 7, 8. Results show that proposed algorithm not only provides optimal net order but also provides more compaction to the escaping nets by utilizing all escape boundary points in a sequence, which can accommodate more nets within the limits of SER Cap .
2) BGA 9x10 Swap pin Scenario-II: In this scenario swap the pin number 6 and 14 with each other in right component of Fig. 10, whereas rest of the things remain exactly the same.The net order remains the same using RDNO algorithm but after placing net number 14 as a first net, it blocks pin number 6 of the right component as shown in Fig. 12 and ends with incomplete routing.However our proposed MBNO algorithm provides a complete routing as shown in Fig. 13, with the following net order: 6, 14, 2, 5, 3, 10, 4, 11, 12, 9, 1, 13, 7, 8.   component of Fig. 10, whereas rest of the settings remain exactly the same in both components.The net order remains the same using RDNO algorithm but after placing net number 14 and 6 as a first and second net respectively, it blocks pin number 3 of the left component as shown in Fig. 14 and ends with an incomplete routing.However our proposed MBNO algorithm first provides the partial routing to the blocked pin i.e. pin number 3, as shown in Fig. 15.Then the algorithm does routing for the pin number 14 and ultimately provides optimal net order for complete routing: 14, 6, 2, 5, 10, 4, 11, 1, 9, 12, 3, 13, 8, 7.
Detailed routing for the given net order is shown in Fig. 16.Results show that how efficiently proposed algorithm solves the SER problem based on the mobility values for each pin.4) Varying Size BGA's Scenario-IV: The scenarios discuss so far are variations of the same example having two BGA components of the same size.Now consider another example having different size BGA s.Component 1 is of size 18x9 and component 2 is of size 17x6.There are 18 nets that need SER connectivity.Again assume single side escape with Orthogonal Cap equals to 1 and the Diagonal Cap is 2. Fig. 17 shows, that the proposed algorithm generates the optimal net order for successful completion of SER for all the nets.
Here, results have been compared by different methods discussed so far.Proposed MBNO algorithm performed 100% routing in all of the four scenarios by generating optimal net order, however RDNO [25] could not route all nets in Scenario-II, Scenario-III and Scenario-IV as shown in Table II.It is important to note that manual routing of even single net left out by an automated method is very difficult to route and is a very time consuming process requiring rearranging of all the routed nets.It is also clear from the results that based on the mobility values of each pin there are better routing results because it avoids any connectivity pin blockage while finding out the next net in the optimal net order.

VI. CONCLUSION
This research work propose the use of net order, in order to solve the SER problem in a way superior to the previous state of art methods.A mobility based net ordering algorithm has been proposed that finds the optimal net order and converts the problem of SER into two simpler problems of finding an ordered escape routing for each component separately.Once "connectivity pins" escape from each component, according to the net order obtained by the proposed algorithm, then area routing becomes quite simple by connecting nets of both components in an order preserving way.Net order obtained by proposed algorithm for 12 representative and randomly generated scenarios has been validated and compared it with the net order obtained by Proteus auto router.Proposed ILP optimization model has been updated to get the detail routing results.The detailed routing results are similar with the results obtained by Proteus auto router.The time for SER optimization model is exponential, i.e., O(2 N E ).Where N is the number of nets that needs to be routed and E is the set of all type of edges.This means addition of only one more variable (net or edge), doubles the computation time due to exponential behaviour, i.e., O(2 N E+1 ).Similarly by decreasing the edges results in exponential reduction in time.In this case, edges are being reduced to almost half (assuming both components have equal edges).Therefore the new time is O(2 N E/2 )+O(2 N E/2 ) for ordered escape routing of both components.This time is much lesser than O(2 N E ) due to exponential reduction.Results shows that proposed algorithm finds routable net order for all scenarios whereas previous algorithm fails to route all nets according to their derived net order.

SER
Cap : Simultaneous Escape Routing capacity.BoundaryP ins Ci : Number of pins on Escape boundary line which needs connectivity for the component Ci.U RDF M obility P i : Number of nets that can pass from Up, Rear, Down and Front side of pin P i. then Routing not possible' and exit 5: P ins C1 [n] ⇐ 'n' Connectivity pins of component 1 6: P ins C2 [n] ⇐ 'n' Connectivity pins of component 2 7:

3 :
if there are multiple pins in a single row then 4:if there are multiple pins in the first row then 5:

8 :
else if there is a pin on the non-escape boundary column and the number of escape boundary points are greater than the number of pins above that row then 9: select this pin first and name it as prioritized rear boundary pin.10: else if In cases, where the same multiple pins are in a single row in both components then 11:

14 : 4 . 2 :
Now there are two separate columns having number of rows equals to the number of pins.This is called initial net ordering that facilitates in finding the final net ordering.Connect pin in the left column with its corresponding pin in the right column with edges as shown in the last step of Fig. Algorithm 4 URDF Mobility Values Algorithm 1: procedure URDF MOBILITY VALUES(P ins Ci [n]) Find the Up, Rear, Down and Front (U RDF ) mobility values of a pin by identifying its position in the grid.3: U = i, R = j, D = k and F = l implies that there are (i/Orthogonal Cap ) number of rows on the up side of the connectivity pin, (i/Orthogonal Cap ) number of columns on the rear side, (k/Orthogonal Cap ) number of rows on the down side and (l/Orthogonal Cap ) number of columns on the front side (escape side) of the pin respectively, in a component.These values help in finding the number of nets that can possibly be passed through, from that side of the pin.According to the example of Fig. 3, Pin-1 is in second row and third column of the left component, which implies that there are one row on the upside of the pin, four rows on the down side, two columns on the rear side and one column on the front side.Since Orthogonal Cap = 1 is being considered, therefore the U RDF values are U = (No. of rows on Up side *Orthogonal Cap ) = 1, R = 2, D = 4 and F = 1 respectively as shown in Fig. 5. Furthermore, U = 1 implies that only one net can pass through the upside of Pin-1 and similarly for the other values.

4 :if
Escape boundary connectivity pins are already fixed with their escape boundary points then 5:

6 : 8 :
else if A and B both have the same position in the corresponding ordering of pins of the two components and no other pin is being blocked by routing this net then 7: these pins are already in order.Only need to update the mobility values of the left over unordered pins.If, by this choice, any pin is being blocked then reselect that pin first.else if A or B is a prioritized rear boundary pin then 9:

10 :
else if If A or B is not in the component's first row and the next row pin (w.r.t current row) of both columns are the same i.e C then

19 :
if routing is not possible by selecting Pin-A and still Pin-B remians then 20: select Pin-B and goto Step 15 21:if routing is not possible by selecting any pin A or B then

TABLE I .
VALIDATION RESULTS AND COMPARISON WITH PROTEUS

TABLE II .
EXPERIMENT RESULTS AND COMPARISON WITH RDNO ALGORITHM