FPGA based Hardware-inthe-Loop Simulation for Digital Control of Power Converters using VHDL-AMS

This paper presents a new approach for complex system design, allowing rapid, efficient and low-cost prototyping. Using this approach can simplify designing tasks and go faster from system modeling to effective hardware implementation. Designing multi-domain systems require different engineering competences and several tools, our approach gives a unique design environment, based on the use of VHDL-AMS modeling language and FPGA device within a single design tool. This approach is intended to enhance hardware-in-the-loop (HIL) practices with a more realistic simulation which improve the verification process in the system design flow. This paper describes the implementation of a software/hardware platform as effective support for our methodology. The feasibility and the benefits of the presented approach are demonstrated through a practical case study of a power converter control. The obtained results show that the developed method achieves significant speed-up compared with conventional simulation methods, using minimum resources and minimum latency. Keywords—Hardware-in-the-Loop (HIL) simulation; FieldProgrammable Gate Array (FPGA); VHDL-AMS; power converter; digital controller


I. INTRODUCTION
In a top-down development process, design tasks are critical keys in system implementation success.In technologic research or industry fields, such as electronic, automation or mechatronic, designing system details go through different steps of analysis and modeling [1], where modeling consists in developing abstract descriptions of some physical realities in such a way that they are useful for the design process [2].Conceived models are then used as an input to a specific simulator to study systems behavior or to explore unconsidered functionalities.
Modeling at different levels of abstraction of multi-domain systems needs the use of different methodologies and tools that should manage mixed-signal design and hardware/software challenges.For that reason, mixed-signal hardware description languages such as VHDL-AMS are indispensable, it is intended to provide a unifying trend that will link the various tasks of analog and mixed-signal design in a coherent framework to support different design methodologies and different design tools [2], [3].
On another side, Verification and validation (V&V) procedures are the solutions for a system design success, they go along with each step of the development cycle.Different techniques can be used to perform those procedures.Usually, it depends on system architecture and hardware implementation.In different engineering systems such automotive, mechatronic or control systems, best practice for V&V requests the construction of a real prototype to test the whole system or one element of the system such as a new control algorithm [4].This prototype is subjected to several cycles of testing and re-design in an expensive facility [5].
Therefore, hardware-in-the-loop (HIL) methods emerge in system design to be an effective way to resolve that issue.HIL methods seem to be an effective alternative to accelerate verification through a specific and relatively low-cost equipment, that permit to finally build a real and an operational prototype [6], [7].
In this paper, an original method for HIL simulation is presented, this method is proposed to simplify and accelerate systems design.This method is based on analog and mixedsignal (AMS) languages and programmable devices.The idea is to use the same hardware description language to model the digital part and the analog part of an AMS system, the digital component (essentially control procedure) is then implemented in FPGA, and the analog part is simulated through the use of VHDL-AMS and dedicated simulation software.This paper is organized as follows.Section 2 introduces the essential of our approach that includes a short description of the context of each contribution of this work.Section 3 presents the implementation aspect of FPGA prototyping.Then, section 4 describes an application case to test and to show the benefits of the effective implementation of our method, where DC/DC converter is modeled in VHDL-AMS and controlled via a digital Proportional-Integral-Derivative (PID) regulator implemented in FPGA.The last section states the conclusion and summarizes the most salient features of our contribution.

II. DESIGN APPROACH
Modeling and simulating a multi-domain system need the use of dedicated tools that can perform multi-abstraction simulation, functional prototyping, verifications, and validations.In the present work, those different design phases would be done through the use of FPGA device and VHDL-AMS modeling language.
In this work, VHDL-AMS is used as the mainstay for the system design; it will be used as a support language for modeling and simulation in the different phases of the system design flow.VHDL-AMS is an extension of the IEEE standard VHDL language, this language allows designers to model any mixed-signal plant that can be described by a system of differential and algebraic equations (DAE's), it supports the hierarchical description and the simulation of continuous and mixed continuous/discrete systems with conservative and nonconservative semantics [2], [8].
VHDL-AMS design requests a simulation process that involves a combined simulation between the analog part and the digital part of an AMS plants model.This is done through data communication and synchronization between a discrete-time and continuous-time simulator engines.In most applications which use VHDL-AMS, the digital side which is VHDL is usually excluded from the design or used only for behavioral simulation, and the analog facet of VHDL-AMS is the only one highlighted part [9]- [12].In the present work, we will take advantages of VHDL to enhance VHDL-AMS design and vice versa, this is done through the validation of the following two points: • Using VHDL-AMS for mixed systems modeling for pure simulation and verification.
• Using VHDL-AMS to develop FPGA application, in order to make a functional simulation, hardware implementation, and verification.
The second part of our design approach is using FPGA based hardware-in-the-loop techniques for test and verification.Usually, FPGAs are used when we need fast processing and parallel computing.Currently, they are also used for system rapid prototyping and system verification, where they take an important part on hardware-in-the-loop platforms.Several works have been recently proposed for FPGA based hardwarein-the-loop [13]- [18], where FPGA benefits are highlighted to simplify and accelerate considerably hardware-in-the-loop simulation.This technique is increasingly used in the development of system control in several fields of application.Therefore, in this paper, we introduce a new method to use hardware-in-the-loop techniques, where FPGA device is associated with a simulation software to make an online simulation with VHDL-AMS model as resumed in Figure 1.
In order to reach our goal, we have to find the best way to bring together FPGA prototyping and VHDL-AMS modeling in an advanced software/hardware simulation platform.

A. VHDL-AMS Simulator
As mentioned in the last section, carrying out our approach need the use of a software which can perform VHDL-AMS simulation and have the ability to communicate with other applications.SMASH software from Dolphin integration is chosen to execute our approach, this software can support the full IEEE VHDL-AMS standard and a set of other modeling languages [19], [20].Moreover, SMASH integrates an application programming interface (API) which gives functions and services to customize and to control simulation running.

B. The Software Application
To perform a hardware-in-the-loop simulation using VHDL-AMS, we have to control the simulation process through the SMASH API.According to Figure 3, a C++ application is built to allow data exchange between simulated models and the FPGA development board, this application performs the following tasks: • The first task that should be accomplished is controlling the simulation process, so the application will be able to collect data from the simulated models and have to force signals values during simulation runs.
• The second task is to transfer data from and to the FPGA Board.Data collected from the simulator are assembled in one datagram then transferred in an UDP/IP packet to the FPGA through the Ethernet link.Afterward, the application is placed in listening mode and awaiting a response from the FPGA.When received, the datagram is unwrapped to extract the needed data to force new signals values, and to allow SMASH to continue the simulation running.
• The last performed task is to synchronize and to manage data exchange between the simulator and the FPGA board.

C. FPGA Implementation
In the present approach, the HIL simulation does not require a sophisticated FPGA board, it simply needs a lowperformance device with an Ethernet interface.To achieve the needed functionalities, a minimum configuration has to be implemented in the FPGA device as depicted in Figure 4. To build a reconfigurable and an evolvable FPGA implementation, the AXI interconnection is used as the basement of our design, with a large number of compatible AXI IP core, we can extend our design to execute other useful functions.Moreover, it can integrate a processor core which is able to execute different control algorithms.
As described in Figure 4, the minimum configuration includes four essential blocks, that are:

A. Case Study
To illustrate our concept and bring out its benefits on system design, a typical example of an electronic power system is used.As shown in Figure 5, the used system consists of a buck power converter with a closed loop controller; this power converter is a typical example of AMS systems, it involves analog and digital behavior and can include other comportments from other disciplines like a thermal behavior or mechanical drive.
As depicted in Figure 5, a voltage sensor gets the digital value of the output voltage, this value is then compared to the reference voltage Vref which generates an error signal e(k) ready at the input of the Proportional-Integral-Derivative (PID) controller.The PID controller makes the feedback loop to regulate the output voltage across the load resistor (R).In this case, the PID runs continuously to generate a duty-cycle u(k) that control the PWM generator to drive the transistor switch (SW).The simplest digital form of the PID controller in the discrete-time domain algorithm is given by the equation below: Where the controller input e(t) is the difference between the reference and the load voltage, and u(t) is the controller output.The three parameters K p , K i , and K d represent proportional, integrator and derivative gain coefficients.For a digital implementation, we are more interested in the discrete-time domain formula, this is given by the equation (2). Where: T s , and T s is the sampling period.In this work, a structural description is used to make a simulation model, each part of the system is designed in different levels of abstraction, depending on the needed accuracy and the complexity in each model.The analog part of the system is modeled in VHDL-AMS and the controller is initially described in VHDL-AMS, then a VHDL code is built to be finally implemented in FPGA.
To build a valid VHDL code intended for an FPGA implementation, first, we have to rearrange the code to make a synthesizable VHDL description according to the available FPGA resources [22].when verified, the PID blocks are assembled with the others needed blocks for the HIL process, then timing constraints are checked for the final implementation.At this stage, an important issue is to be considered, a binary format representation of digital data has to be set, we choose a 32-bit fixed point format for input/output signals of the digital controller.

B. VHDL-AMS Simulation
First of all, the whole system is modeled in VHDL-AMS including system parameters as shown in Table I, the system is then simulated in a mixed signal mode with a variable time step, where each part of the system is verified with different scenarios especially the digital controller model.
The simulation waveforms depicted in the Figure 6.a shows the load voltage value for variable voltage reference; the result allows us to verify that the digital controller draws the output voltage of the analog buck converter according to the input reference.Also, in Figure 6.b we can see the different signals involved in the functioning of the digital PID such as the clock, Error, voltage signal...etc.

C. FPGA Simulation and Verification
In order to validate our approach, we perform numerous tests using the developed platform based on FPGA and VHDL-AMS simulator.The hardware part can be implemented in any FPGA development board that includes an Ethernet PHY.To be consistent with our objectives, we consider a low-cost development board; an Avnet LX9 MicroBoard embedding  a Xilinx Spartan-6 FPGA, which is suitable for low-budget design (Figure 7).
After programming the FPGA, the developed software application is executed, then SMASH software loads the plant model.After initializing the software parameters and the UDP/IP Ethernet communication channel, the user can begin the HIL simulation using a VHDL-AMS testbench, this last generates the necessary signals for the different test scenarios.
To compare efficiently software simulation and FPGA based HIL simulation, the same simulator parameters as for pure VHDL-AMS simulation (presented in the last section) are applied.Experimental results are obtained with a 100Mb/s Ethernet channel and data are transferred to, and from the FPGA board as vectors of 32 bits, and the FPGA is running at 100MHz.For the test validation, the same scenarios are considered as used for the previous simulation.The Figure 8.a shows the result of FIL simulation, where the load voltage waveform is identical to the software simulation.In the zoomed view

D. FPGA Resources
Table II lists the FPGA resources used to implement the needed components, consumed resources depend on the used FPGA technology, and proportions are referred to the available resources of a Spartan-6 XC6SLX9.
In this table, the AXI Ethernet lite module is a Xilinx generated core which provides the Ethernet interface, the PID dig represents the digital controller part, and the third component refers to the supervisor part that is necessary to connect and control all needed components via an AXI bus.
The global utilization of LUT represents only 16,2% of the available LUT, and the integration of the PID controller represent only 3,8%, those results show that the proposed HIL platform don't need large FPGA resources, and with the actual FPGA device there are enough resources to replace the digital PID with a more complex controller or to add other modules for additional functionalities.

E. Timing Performance
To bring out the benefits of the implementation of our approach in terms of time processing, several simulation scenarios are performed in software mode and in FPGA mixed mode with a variable simulation time step.The simulation times have been measured using a 2.5 GHz Intel Core i5 with 4 GB of RAM memory.The needed simulation time is significantly reduced (about 80%).This is due to the fact that software mixed simulation uses big CPU resources for digital simulation, while in our approach; the digital simulation is exclusively achieved by the FPGA device.
On the other hand, we measured the time latency for different simulation cases.We note that the latency for network transmission and processing within the FPGA is about 55µs and the latency for software processing is about 2 5ms.Improving hardware and software latency for a specific application case can lead to real-time hardware-in-the-loop simulation.

V. CONCLUSION
The work exposed in this paper focuses on the presentation of a new approach for simulation and verification of complex systems.With this goal in mind, this work introduces a unique design tool for hardware-in-loop simulation based on FPGA and VHDL-AMS.Thereby, benefits of VHDL-AMS mixed design and FPGA rapid prototyping are combined together to improve system design and to allow fast design development time and a short time to market.
In order to validate our approach and to demonstrate its effectiveness, results of the implementation and simulation of a regulated power converter are presented, where the digital controller is coded using VHDL language then implemented in FPGA and the rest of the system is simulated on a host PC using VHDL-AMS models.The studied application gives an overview of the capabilities of this method to accomplish multiple design benefits, where several experiences have been achieved shown a significant reduction of simulation processing time and a low latency for data transfer.On another hand, hardware resources are minimized, to match any low-cost FPGA development board for a high-reliability simulation.

Fig. 2 .
Fig. 2. Simplified representation for the proposed platform

Fig. 4 .
Fig. 4. Implementation of the hardware controller in the FPGA

1 )
Ethernet MAC (Media Access Controller): Many Ethernet controller cores can be used, it depends on several parameters like the targeted FPGA, connection speed or channel protocol.The proposed platform uses AXI Ethernet lite MAC from Xilinx[21], it provides an efficient Ethernet interface with least resources and can be configured to operate at the rate of 100Mb/s.2) AXI Master: This module is written in VHDL, it follows the AXI protocol and provides signals to perform read/write operations in the AXI bus, this is done to control the Ethernet module.On the other side, this module exchange data with the user controller module.3) User IP Controller: This is the implementation of the digital controller under test.4) Supervisor: This module manages all the operations executed by the overmentioned modules.The supervisor works under the control of a finite state machine (FSM).The FSM provides control signals to manage and synchronize data transaction between the different modules.

Fig. 5 .
Fig. 5. Buck power converter structure with PID control loop
Fig. 8. HIL simulation waveforms (a) Voltage load and voltage error for variable voltage reference (b) PID digital signals.

TABLE I .
SYSTEM PARAMETERS

Table
III summarises the CPU time and the logic kernel time required to perform for the different scenarios.Those scenarios simulate the same design for different simulation times and for different switching frequencies, this implies a different volume of analog and discrete-time simulation points which demand various hardware resources.