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Digital Object Identifier (DOI) : 10.14569/IJACSA.2013.040118
Article Published in International Journal of Advanced Computer Science and Applications(IJACSA), Volume 4 Issue 1, 2013.
Abstract: In this paper, we proposed an area-efficient carry select adder by sharing the common Boolean logic term. After logic simplification and sharing partial circuit, we only need one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation. Through the multiplexer, we can select the correct output result according to the logic state of carry-in signal. In this way, the transistor count in a 32-bit carry select adder can be greatly reduced from 1947 to 960.
Garish Kumar Wadhwa, Amit Grover, Neeti Grover and Gurpreet Singh, “An Area-Efficient Carry Select Adder Design by using 180 nm Technology” International Journal of Advanced Computer Science and Applications(IJACSA), 4(1), 2013. http://dx.doi.org/10.14569/IJACSA.2013.040118