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International Journal of Advanced Computer Science and Applications(IJACSA), Volume 4 Issue 1, 2013.
Abstract: In this paper, we proposed an area-efficient carry select adder by sharing the common Boolean logic term. After logic simplification and sharing partial circuit, we only need one XOR gate and one inverter gate in each summation operation as well as one AND gate and one inverter gate in each carry-out operation. Through the multiplexer, we can select the correct output result according to the logic state of carry-in signal. In this way, the transistor count in a 32-bit carry select adder can be greatly reduced from 1947 to 960.
Garish Kumar Wadhwa, Amit Grover, Neeti Grover and Gurpreet Singh, “An Area-Efficient Carry Select Adder Design by using 180 nm Technology” International Journal of Advanced Computer Science and Applications(IJACSA), 4(1), 2013. http://dx.doi.org/10.14569/IJACSA.2013.040118
@article{Wadhwa2013,
title = {An Area-Efficient Carry Select Adder Design by using 180 nm Technology},
journal = {International Journal of Advanced Computer Science and Applications},
doi = {10.14569/IJACSA.2013.040118},
url = {http://dx.doi.org/10.14569/IJACSA.2013.040118},
year = {2013},
publisher = {The Science and Information Organization},
volume = {4},
number = {1},
author = {Garish Kumar Wadhwa and Amit Grover and Neeti Grover and Gurpreet Singh}
}
Copyright Statement: This is an open access article licensed under a Creative Commons Attribution 4.0 International License, which permits unrestricted use, distribution, and reproduction in any medium, even commercially as long as the original work is properly cited.