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Digital Object Identifier (DOI) : 10.14569/IJACSA.2013.040335
Article Published in International Journal of Advanced Computer Science and Applications(IJACSA), Volume 4 Issue 3, 2013.
Abstract: The basic sensor node architecture in a wireless sensor network contains sensing, transceiver, processing and memory units along with the power supply module. Because the basic sensor network application nature is surveillance, these networks may be deployed in a remote environment without human intervention. The sensor nodes are also battery-powered tiny devices with limited memory capacity. Because of these sensor node limitations, the architecture can be modified to efficiently utilise energy during memory accesses by dividing the memory into multiple banks and including a memory switching controller unit and a power switching module. This modification conserves energy, so power can be supplied only to the bank or part of the memory being accessed instead of powering the entire memory module, thus leading to efficient energy consumption. Simulations have been performed on fragmented memory architecture by incorporating the M/M/1 queuing model. When the packets get queued up, energy utilisation and a packet drop at the sensor node is observed. The energy consumption is reduced by an average of 70%, and there is significantly less packet drop compared to the normal memory architecture. This leads to increase in node and network lifetime and prevents information loss
Harish H Kenchannavar, M.M.Math and Umakant P.Kulkarni, “Energy-Aware Fragmented Memory Architecture with a Switching Power Supply for Sensor Nodes” International Journal of Advanced Computer Science and Applications(IJACSA), 4(3), 2013. http://dx.doi.org/10.14569/IJACSA.2013.040335