Copyright Statement: This is an open access article licensed under a Creative Commons Attribution 4.0 International License, which permits unrestricted use, distribution, and reproduction in any medium, even commercially as long as the original work is properly cited.
Digital Object Identifier (DOI) : 10.14569/IJACSA.2014.050212
Article Published in International Journal of Advanced Computer Science and Applications(IJACSA), Volume 5 Issue 2, 2014.
Abstract: With semiconductor industry trend of “smaller the better”, from an idea to a final product, more innovation on product portfolio and yet remaining competitive and profitable are few criteria which are culminating into pressure and need for more and more innovation for CAD flow, process management and project execution cycle. Project schedules are very tight and to achieve first silicon success is key for projects. This necessitates quicker verification with better coverage matrix. Quicker Verification requires early development of the verification environment with wider test vectors without waiting for RTL to be available. In this paper, we are presenting a novel approach of early development of reusable multi-language verification flow, by addressing four major activities of verification – 1. Early creation of Executable Specification 2. Early creation of Verification Environment 3. Early development of test vectors and 4. Better and increased Re-use of blocks Although this paper focuses on early development of UVM based Verification Environment of Image Signal Processing designs using TLM Reference Model of RTL, same concept can be extended for non-image signal processing designs.
Abhishek Jain, Sandeep Jana, Dr. Hima Gupta and Krishna Kumar, “Early Development of UVM based Verification Environment of Image Signal Processing Designs using TLM Reference Model of RTL” International Journal of Advanced Computer Science and Applications(IJACSA), 5(2), 2014. http://dx.doi.org/10.14569/IJACSA.2014.050212