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Digital Object Identifier (DOI) : 10.14569/IJACSA.2015.060406
Article Published in International Journal of Advanced Computer Science and Applications(IJACSA), Volume 6 Issue 4, 2015.
Abstract: The purpose of this paper is to describe an predictable CPU architecture, based on the five stage pipeline assembly line and a hardware scheduler engine. We aim at developing a fine-grained multithreading implementation, named nMPRA-MT. The new proposed architecture uses replication and remapping techniques for the program counter, the register file, and the pipeline registers and is implemented with a FPGA device. An original implementation of a MIPS processor with thread interleaved pipeline is obtained, using dynamic scheduling of hard real-time tasks and interrupts. In terms of interrupts handling, the architecture uses a particular method consisting of assigning interrupts to tasks, which insures an efficient control for both the context switch, and the system real-time behavior. The originality of the approach resides in the predictability and spatial isolation of the hard real-time tasks, executed every two clock cycles. The nMPRA-MT architecture is enabled by an innovative scheme of predictable scheduling algorithm, without stalling the pipeline assembly line.
Nicoleta Cristina GAITAN, Ionel ZAGAN and Vasile Gheorghita GAITAN, “Predictable CPU Architecture Designed for Small Real-Time Application - Concept and Theory of Operation” International Journal of Advanced Computer Science and Applications(IJACSA), 6(4), 2015. http://dx.doi.org/10.14569/IJACSA.2015.060406