Thread-Sensitive Shared Instruction Cache Analysis for Precise WCET Estimation of Multithreaded Programs

Abstract: Real-time systems require strict adherence to task deadlines, making Worst-Case Execution Time (WCET) analysis essential. WCET estimation typically involves static analysis of instructions in a program, making use of models of hardware and architectural units such as shared instruction caches that are as precise as possible. Shared instruction caches pose a challenge because cache behaviour depends on access history and inter-core interference in multicore systems. Existing approaches do not fully exploit thread lifecycle and synchronization semantics when modeling shared instruction cache behavior. In contrast, the proposed TP-WCIP model explicitly incorporates these semantics to eliminate infeasible interference scenarios. By confining interference placement to feasible concurrent execution regions, it achieves more precise WCET estimation. Worst-case latency, due to shared instruction cache accesses in the presence of inter-core interferences, is estimated for each thread in a multithreaded program with a focus on start, join, and synchronization (wait and notify) primitives. A highly precise model, termed Threaded Program Worst-Case Interference Placement (TP-WCIP), is proposed for the static analysis of multithreaded programs to estimate Worst-Case Execution Time (WCET). The proposed model is evaluated in comparison with Cache Block Conflict Number (CCN), Worst-Case Interference Placement (WCIP), and Interference Partitioning (IP). TP-WCIP exploits concurrency and happens-before relationships induced by start, join, and synchronization primitives to accurately characterize inter-core interferences. The TP-WCIP model for shared instruction cache analysis is validated using benchmark programs and compared against approaches reported in the literature. It is established both theoretically and experimentally that the proposed model TP-WCIP leads to more precise worst-case latency measurements. Result analysis of benchmark programs Papabench and extended Mälardalen benchmarks shows that the TP-WCIP model reduces interferences by up to 27% over IP, 53% over WCIP, and 75% over CCN, while preserving up to 16% more Shared Instruction Cache Hits than IP, 48% than WCIP, and 84% than CCN, thereby delivering more precise static WCET estimates for multi-threaded programs on multicore architectures.

Naveeta Rani, P Padma Priya Dharishini and PVR Murthy. “Thread-Sensitive Shared Instruction Cache Analysis for Precise WCET Estimation of Multithreaded Programs”. International Journal of Advanced Computer Science and Applications (IJACSA) 17.3 (2026). http://dx.doi.org/10.14569/IJACSA.2026.0170376

@article{Rani2026,
title = {Thread-Sensitive Shared Instruction Cache Analysis for Precise WCET Estimation of Multithreaded Programs},
journal = {International Journal of Advanced Computer Science and Applications},
doi = {10.14569/IJACSA.2026.0170376},
url = {http://dx.doi.org/10.14569/IJACSA.2026.0170376},
year = {2026},
publisher = {The Science and Information Organization},
volume = {17},
number = {3},
author = {Naveeta Rani and P Padma Priya Dharishini and PVR Murthy}
}