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DOI: 10.14569/IJACSA.2026.0170493
PDF

A Survey of FPGA Floorplanning for Dynamic Partial Reconfiguration: From Heuristic Approaches to Autonomous AI-Driven Methods

Author 1: Ibrahim LIMEM
Author 2: Sadok BAZINE
Author 3: Abdessalem BEN ABDELALI

International Journal of Advanced Computer Science and Applications(IJACSA), Volume 17 Issue 4, 2026.

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Abstract: Dynamic Partial Reconfiguration (DPR) has emerged as a key enabler of runtime adaptability and hardware-software co-design in modern FPGA-based heterogeneous systems. However, with the transition toward 5nm technologies and multi-die 3D-IC architectures, spatial resource management faces a “complexity wall,” where traditional manual floorplanning techniques struggle to satisfy timing, utilization, and scalability constraints. This study presents a systematic literature review and proposes a comprehensive taxonomy of FPGA floorplanning and placement methodologies developed over the past two decades. The proposed classification organizes existing approaches into three generations: 1) the Heuristic Era, focused on rule-based automation and physical feasibility; 2) the Optimization Era, characterized by formal mathematical models and Mixed-Integer Linear Programming (MILP) for heterogeneous resource allocation; and 3) the Autonomous Era, which leverages AI-driven techniques, including Reinforcement Learning and intelligent scheduling, to enable predictive and shape-adaptive placement strategies. This evolution reflects a fundamental shift from static grid-based management toward elastic, self-optimizing FPGA fabrics. We further examine emerging architectural constraints, including Super Logic Region (SLR) boundaries and hierarchical nested Partial Reconfigurable Regions (PRRs). Beyond this taxonomy, the survey identifies a critical scalability–optimality trade-off, highlighting the need for hybrid frameworks that combine the formal guarantees of optimization-based methods with the real-time adaptability of AI-driven approaches. It further establishes a unifying perspective in which DPR is evolving from a logic-reconfiguration mechanism into a thermal–spatial management paradigm for mitigating heat in high-density 3D-IC systems. Finally, the analysis reveals a significant functional–physical gap in current autonomous design tools, emphasizing the need for context-aware agents capable of jointly reasoning about temporal task dependencies and spatial floorplanning constraints. This review provides a structured roadmap for the development of next-generation intelligent control frameworks for edge and cloud-scale reconfigurable computing systems.

Keywords: Field Programmable Gate Arrays (FPGA); Floor-planning; Dynamic Partial Reconfiguration (DPR); bitstream relocation; hardware autonomy; reinforcement learning; heterogeneous computing; 2D shape-adaptive placement

Ibrahim LIMEM, Sadok BAZINE and Abdessalem BEN ABDELALI. “A Survey of FPGA Floorplanning for Dynamic Partial Reconfiguration: From Heuristic Approaches to Autonomous AI-Driven Methods”. International Journal of Advanced Computer Science and Applications (IJACSA) 17.4 (2026). http://dx.doi.org/10.14569/IJACSA.2026.0170493

@article{LIMEM2026,
title = {A Survey of FPGA Floorplanning for Dynamic Partial Reconfiguration: From Heuristic Approaches to Autonomous AI-Driven Methods},
journal = {International Journal of Advanced Computer Science and Applications},
doi = {10.14569/IJACSA.2026.0170493},
url = {http://dx.doi.org/10.14569/IJACSA.2026.0170493},
year = {2026},
publisher = {The Science and Information Organization},
volume = {17},
number = {4},
author = {Ibrahim LIMEM and Sadok BAZINE and Abdessalem BEN ABDELALI}
}



Copyright Statement: This is an open access article licensed under a Creative Commons Attribution 4.0 International License, which permits unrestricted use, distribution, and reproduction in any medium, even commercially as long as the original work is properly cited.

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