Low-Latency FPGA-Based PCA Acceleration for Hyperspectral Image Dimensionality Reduction

Remote sensing systems generate large volumes of high-dimensional data, which creates significant challenges for onboard processing and data transmission under computational, memory, and energy constraints. Dimensionality reduction is therefore essential for enabling efficient embedded remote sensing applications. This work presents a hardware-accelerated implementation of Principal Component Analysis (PCA) on an FPGA platform for low-latency onboard data reduction. A hardware–software co-design methodology is adopted and implemented using the Vivado design flow on an Xilinx FPGA. The proposed architecture focuses on accelerating the most computationally intensive stage of PCA while preserving the most informative components of the input data. Experimental evaluations demonstrate that the FPGA-based implementation achieves a 2.8× speedup while reducing energy consumption by 72.4% compared with an ARM-only software implementation, while maintaining efficient hardware resource utilization. These results confirm the suitability of the proposed accelerator for low-latency, energy-efficient onboard dimensionality reduction in resource-constrained remote sensing systems.

@article{Fredj2026,
  title     = {Low-Latency FPGA-Based PCA Acceleration for Hyperspectral Image Dimensionality Reduction},
  journal   = {International Journal of Advanced Computer Science and Applications},
  volume    = {17},
  number    = {7},
  year      = {2026},
  publisher = {The Science and Information Organization},
  author    = {Hana Ben Fredj and Ahlem kehili and Amani Chabbeh and Jamel Baili and Chokri Souani},
  doi       = {10.14569/IJACSA.2026.0170764},
  url       = {https://doi.org/10.14569/IJACSA.2026.0170764}
}