Hardware-Software Co-Design of K-Means Clustering on Zynq FPGAs via OpenCL

Clustering algorithms such as K-means are widely employed in machine learning and data analytics; however, their computational complexity becomes a significant limitation when applied to large-scale or latency-sensitive workloads. To over-come this challenge, this study presents a hardware-accelerated K-means clustering implementation using Field-Programmable Gate Arrays (FPGAs) within the Open Computing Language (OpenCL) framework. The proposed architecture leverages the fine-grained parallelism of FPGAs to accelerate the assignment phase, which is dominated by repetitive distance computations between data points and centroids. The proposed heterogeneous architecture accelerates only the assignment stage of the K-means algorithm on the FPGA, while the centroid update and convergence-control stages remain executed on the embedded ARM Cortex-A9 processor. Experimental results obtained on a two-dimensional synthetic floating-point dataset demonstrate significant performance gains over a CPU-only implementation, achieving speedups of up to 39× in execution time. The results also indicate consistent and favorable scalability trends across the evaluated synthetic two-dimensional configurations. To further assess the generalizability of the proposed approach, the accelerator was additionally validated on a real-world geospatial dataset, confirming consistent performance gains beyond synthetic benchmarks.

@article{JABALLI2026,
  title     = {Hardware-Software Co-Design of K-Means Clustering on Zynq FPGAs via OpenCL},
  journal   = {International Journal of Advanced Computer Science and Applications},
  volume    = {17},
  number    = {7},
  year      = {2026},
  publisher = {The Science and Information Organization},
  author    = {Eya JABALLI and Soufien GDAIM and Noureddine LIOUANE},
  doi       = {10.14569/IJACSA.2026.0170775},
  url       = {https://doi.org/10.14569/IJACSA.2026.0170775}
}