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Research Article | Open Access |

VHDL Design and FPGA Implementation of a Parallel Reed-Solomon (15, K, D) Encoder/Decoder

Author 1: Mustapha ELHAROUSSI Author 2: Asmaa HAMYANI Author 3: Mostafa BELKASMI
International Journal of Advanced Computer Science and Applications (IJACSA) · Vol. 4, No. 1 · Published 2013 · Cited by 7

DOI: https://doi.org/10.14569/IJACSA.2013.040105

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Abstract

In this article, we propose a Reed Solomon error correcting encoder/decoder with the complete description of a concrete implementation starting from a VHDL description of this decoder. The design on FPGA of the (15, k, d) Reed Solomon decoder is studied and simulated in order to implement an encoder/decoder function.The proposed architecture of the decoder can achieve a high data rate, in our case, 5 clock cycles, and having a reasonable complexity (1010 CLBs).

Keywords

Error detecting correcting codes Reed-Solomon encoder/decoder VHDL language FPGA

How to Cite this Article

ELHAROUSSI, M., HAMYANI, A., & BELKASMI, M. (2013). VHDL Design and FPGA Implementation of a Parallel Reed-Solomon (15, K, D) Encoder/Decoder. International Journal of Advanced Computer Science and Applications, 4(1). https://doi.org/10.14569/IJACSA.2013.040105

ELHAROUSSI, Mustapha, et al.. "VHDL Design and FPGA Implementation of a Parallel Reed-Solomon (15, K, D) Encoder/Decoder." International Journal of Advanced Computer Science and Applications, vol. 4, no. 1, 2013, https://doi.org/10.14569/IJACSA.2013.040105.

@article{ELHAROUSSI2013,
  title     = {VHDL Design and FPGA Implementation of a Parallel Reed-Solomon (15, K, D) Encoder/Decoder},
  journal   = {International Journal of Advanced Computer Science and Applications},
  volume    = {4},
  number    = {1},
  year      = {2013},
  publisher = {The Science and Information Organization},
  author    = {Mustapha ELHAROUSSI and Asmaa HAMYANI and Mostafa BELKASMI},
  doi       = {10.14569/IJACSA.2013.040105},
  url       = {https://doi.org/10.14569/IJACSA.2013.040105}
}

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