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International Journal of Advanced Computer Science and Applications(IJACSA), Volume 4 Issue 1, 2013.
Abstract: In this article, we propose a Reed Solomon error correcting encoder/decoder with the complete description of a concrete implementation starting from a VHDL description of this decoder. The design on FPGA of the (15, k, d) Reed Solomon decoder is studied and simulated in order to implement an encoder/decoder function.The proposed architecture of the decoder can achieve a high data rate, in our case, 5 clock cycles, and having a reasonable complexity (1010 CLBs).
Mustapha ELHAROUSSI, Asmaa HAMYANI and Mostafa BELKASMI, “VHDL Design and FPGA Implementation of a Parallel Reed-Solomon (15, K, D) Encoder/Decoder” International Journal of Advanced Computer Science and Applications(IJACSA), 4(1), 2013. http://dx.doi.org/10.14569/IJACSA.2013.040105
@article{ELHAROUSSI2013,
title = {VHDL Design and FPGA Implementation of a Parallel Reed-Solomon (15, K, D) Encoder/Decoder},
journal = {International Journal of Advanced Computer Science and Applications},
doi = {10.14569/IJACSA.2013.040105},
url = {http://dx.doi.org/10.14569/IJACSA.2013.040105},
year = {2013},
publisher = {The Science and Information Organization},
volume = {4},
number = {1},
author = {Mustapha ELHAROUSSI and Asmaa HAMYANI and Mostafa BELKASMI}
}
Copyright Statement: This is an open access article licensed under a Creative Commons Attribution 4.0 International License, which permits unrestricted use, distribution, and reproduction in any medium, even commercially as long as the original work is properly cited.