Design of a Content Addressable Memory-based Parallel Processor implementing (-1+j)-based Binary Number System
DOI: 10.14569/SpecialIssue.2014.040302
Abstract
Keywords
How to Cite this Article
Jamil, T. (2014). Design of a Content Addressable Memory-based Parallel Processor implementing (-1+j)-based Binary Number System. International Journal of Advanced Computer Science and Applications, 4(3). https://doi.org/10.14569/SpecialIssue.2014.040302
Jamil, Tariq. "Design of a Content Addressable Memory-based Parallel Processor implementing (-1+j)-based Binary Number System." International Journal of Advanced Computer Science and Applications, vol. 4, no. 3, 2014, https://doi.org/10.14569/SpecialIssue.2014.040302.
@article{Jamil2014,
title = {Design of a Content Addressable Memory-based Parallel Processor implementing (-1+j)-based Binary Number System},
journal = {International Journal of Advanced Computer Science and Applications},
volume = {4},
number = {3},
year = {2014},
publisher = {The Science and Information Organization},
note = {Special Issue on Extended Papers from Science and Information Conference 2014},
author = {Tariq Jamil},
doi = {10.14569/SpecialIssue.2014.040302},
url = {https://doi.org/10.14569/SpecialIssue.2014.040302}
}
Open Access — licensed under a Creative Commons Attribution 4.0 International License. Unrestricted use, distribution, and reproduction in any medium, even commercially, as long as the original work is properly cited.