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Research Article | Open Access |

Real-Time H.264/AVC Entropy Encoder Hardware Architecture in Baseline Profile

Author 1: Ben Hamida Asma Author 2: Dhahri Salah Author 3: Zitouni Abdelkrim
International Journal of Advanced Computer Science and Applications (IJACSA) · Vol. 8, No. 3 · Published 2017

DOI: https://doi.org/10.14569/IJACSA.2017.080339

Abstract

In this paper, we present a new hardware architecture of an entropy encoder for an H.264/AVC video encoder. The proposed design aims to employ a parallel module at a pre-encoding stage to reduce a critical path. Additionally, the arithmetic table elimination method is used to eliminate the memory cost. Besides, the reduction in the size of VLC tables offers area saving. This architecture is synthesized on an FPGA Virtex IV. The simulation results show that this design can operate up to 234 MHz, which allows processing a 4CIF video format in real time.

Keywords

How to Cite this Article

Asma, B. H., Salah, D., & Abdelkrim, Z. (2017). Real-Time H.264/AVC Entropy Encoder Hardware Architecture in Baseline Profile. International Journal of Advanced Computer Science and Applications, 8(3). https://doi.org/10.14569/IJACSA.2017.080339

Asma, Ben Hamida, et al.. "Real-Time H.264/AVC Entropy Encoder Hardware Architecture in Baseline Profile." International Journal of Advanced Computer Science and Applications, vol. 8, no. 3, 2017, https://doi.org/10.14569/IJACSA.2017.080339.

@article{Asma2017,
  title     = {Real-Time H.264/AVC Entropy Encoder Hardware Architecture in Baseline Profile},
  journal   = {International Journal of Advanced Computer Science and Applications},
  volume    = {8},
  number    = {3},
  year      = {2017},
  publisher = {The Science and Information Organization},
  author    = {Ben Hamida Asma and Dhahri Salah and Zitouni Abdelkrim},
  doi       = {10.14569/IJACSA.2017.080339},
  url       = {https://doi.org/10.14569/IJACSA.2017.080339}
}

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