Abstract: Context-Based Adaptive Binary Arithmetic Coding (CABAC) is a well-known bottleneck in H.264/AVC, owing to the highly serialized calculation and high data dependency of the binary arithmetic encoder. This work presents a hardware architecture for the sub-module binary arithmetic encoder of the CABAC. Moreover, a clock gating technique is inserted into our design for power saving. An FPGA design of the proposed architecture can work at a frequency up to 268 MHz on Virtex 5. The suggested design can achieve 17% of power consumption saving, which allows it to be applied for low power video coding applications.

Ben Hamida Asma, Nedra Jarray and Zitouni Abdelkrim, “Low-Power Hardware Design of Binary Arithmetic Encoder in H.264” International Journal of Advanced Computer Science and Applications(IJACSA), 8(7), 2017. http://dx.doi.org/10.14569/IJACSA.2017.080756

@article{Asma2017,
title = {Low-Power Hardware Design of Binary Arithmetic Encoder in H.264},
journal = {International Journal of Advanced Computer Science and Applications}
doi = {10.14569/IJACSA.2017.080756},
url = {http://dx.doi.org/10.14569/IJACSA.2017.080756},
year = {2017},
publisher = {The Science and Information Organization},
volume = {8},
number = {7},
author = {Ben Hamida Asma and Nedra Jarray and Zitouni Abdelkrim},
}