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Research Article | Open Access |

Low-Power Hardware Design of Binary Arithmetic Encoder in H.264

Author 1: Ben Hamida Asma Author 2: Nedra Jarray Author 3: Zitouni Abdelkrim
International Journal of Advanced Computer Science and Applications (IJACSA) · Vol. 8, No. 7 · Published 2017

DOI: https://doi.org/10.14569/IJACSA.2017.080756

Abstract

Context-Based Adaptive Binary Arithmetic Coding (CABAC) is a well-known bottleneck in H.264/AVC, owing to the highly serialized calculation and high data dependency of the binary arithmetic encoder. This work presents a hardware architecture for the sub-module binary arithmetic encoder of the CABAC. Moreover, a clock gating technique is inserted into our design for power saving. An FPGA design of the proposed architecture can work at a frequency up to 268 MHz on Virtex 5. The suggested design can achieve 17% of power consumption saving, which allows it to be applied for low power video coding applications.

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How to Cite this Article

Asma, B. H., Jarray, N., & Abdelkrim, Z. (2017). Low-Power Hardware Design of Binary Arithmetic Encoder in H.264. International Journal of Advanced Computer Science and Applications, 8(7). https://doi.org/10.14569/IJACSA.2017.080756

Asma, Ben Hamida, et al.. "Low-Power Hardware Design of Binary Arithmetic Encoder in H.264." International Journal of Advanced Computer Science and Applications, vol. 8, no. 7, 2017, https://doi.org/10.14569/IJACSA.2017.080756.

@article{Asma2017,
  title     = {Low-Power Hardware Design of Binary Arithmetic Encoder in H.264},
  journal   = {International Journal of Advanced Computer Science and Applications},
  volume    = {8},
  number    = {7},
  year      = {2017},
  publisher = {The Science and Information Organization},
  author    = {Ben Hamida Asma and Nedra Jarray and Zitouni Abdelkrim},
  doi       = {10.14569/IJACSA.2017.080756},
  url       = {https://doi.org/10.14569/IJACSA.2017.080756}
}

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