Low-Power Hardware Design of Binary Arithmetic Encoder in H.264
DOI: https://doi.org/10.14569/IJACSA.2017.080756
Abstract
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How to Cite this Article
Asma, B. H., Jarray, N., & Abdelkrim, Z. (2017). Low-Power Hardware Design of Binary Arithmetic Encoder in H.264. International Journal of Advanced Computer Science and Applications, 8(7). https://doi.org/10.14569/IJACSA.2017.080756
Asma, Ben Hamida, et al.. "Low-Power Hardware Design of Binary Arithmetic Encoder in H.264." International Journal of Advanced Computer Science and Applications, vol. 8, no. 7, 2017, https://doi.org/10.14569/IJACSA.2017.080756.
@article{Asma2017,
title = {Low-Power Hardware Design of Binary Arithmetic Encoder in H.264},
journal = {International Journal of Advanced Computer Science and Applications},
volume = {8},
number = {7},
year = {2017},
publisher = {The Science and Information Organization},
author = {Ben Hamida Asma and Nedra Jarray and Zitouni Abdelkrim},
doi = {10.14569/IJACSA.2017.080756},
url = {https://doi.org/10.14569/IJACSA.2017.080756}
}
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