A Cost-Efficient Look-Up Table based Binary Coded Decimal Adder Design

The Binary Coded Decimal (BCD) being the more accurate and human-readable representation with ease of conver-sion, is prevailing in the computing and electronic communication. In this paper, a tree-structured parallel BCD addition algorithm is proposed with the reduced time complexity O(􀀀􀀀􀀁􀀂􀀃2 􀀁􀀄 􀀅 􀀀􀀀 − 􀀆􀀄􀀄, where 􀀀 = number of digits and 􀀁 = number of bits in a digit. BCD adder is more effective with a LUT (Look-Up Table)-based design, due to FPGA (Field Programmable Gate Array) technology’s enumerable benefits and applications. A size-minimal and depth-minimal LUT-based BCD adder circuit construction is the main contribution of this paper. The proposed parallel BCD adder gains a radical achievement compared to the existing best-known LUT-based BCD adders. The proposed BCD Adder provides prominent better performance with 20.0%reduction in area and 41.32% reduction in delay for the post-layout simulation. Since the proposed circuit is improved both in area and delay parameter, it is 53.06% efficient in terms of area-delay product compared to the best known existing BCD adder, which is surely a significant achievement.

@article{Sworna2018,
  title     = {A Cost-Efficient Look-Up Table based Binary Coded Decimal Adder Design},
  journal   = {International Journal of Advanced Computer Science and Applications},
  volume    = {9},
  number    = {1},
  year      = {2018},
  publisher = {The Science and Information Organization},
  author    = {Zarrin Tasnim Sworna and Mubin Ul Haque and Hafiz Md. Hasan Babu and Lafifa Jamal},
  doi       = {10.14569/SpecialIssue.2018.0901120},
  url       = {https://doi.org/10.14569/SpecialIssue.2018.0901120}
}