Augmented Efficiency of CLA Logic through Multiple CMOS Configurations

Adders are the basic building blocks in the digital systems. Addition is an indispensable operation in digital, analog and control systems. Performance optimization of a digital adder relies on the parameters such as power, speed and area. Much research has been going on in optimizing the delay and power dissipation of adders. Carry-lookahead adder (CLA) is considered one of the fastest digital adders. It emerges from the concept of computing all incoming carriers in parallel. This paper introduces various design implementations using CMOS transistors, producing unique logic of CLA adder. Each design implementation is analyzed by assessing the power dissipation and the delay at every possible state by transistor sizing. Simulations have been performed on Tanner EDA tools based on 250nm technology at 2.5V supply voltage. Previous work on CLA has been examined, and the 8-bit design of CLA and its delay and power dissipation has been evaluated.

@article{Muppaneni2018,
  title     = {Augmented Efficiency of CLA Logic through Multiple CMOS Configurations},
  journal   = {International Journal of Advanced Computer Science and Applications},
  volume    = {9},
  number    = {1},
  year      = {2018},
  publisher = {The Science and Information Organization},
  author    = {Naga Spandana Muppaneni and Steve C.Chiu},
  doi       = {10.14569/SpecialIssue.2018.0901121},
  url       = {https://doi.org/10.14569/SpecialIssue.2018.0901121}
}