Abstract: An improved trapezoidal pile gate bulk FinFET device is implemented with an extension in the gate for enhancing the performance. The novelty in the design is trapezoidal cross-section FinFET with stacked metal gate along with extension on both sides. Such improved device structure with additional process cost exhibits significant enhancement in the performance metrics specially in terms of leakage current behavior. The simulation study proves the suitability of the device for low power applications with improved on/off current ratio, subthreshold swing (SS), drain induced barrier lowering (DIBL), Gate Induced Drain Leakage (GIDL) uniform distribution of electron charge density along the channel and effects of Augur recombination within the channel.

Sangeeta Mangesh, Pradeep Chopra and Krishan K. Saini, “A Trapezoidal Cross-Section Stacked Gate FinFET with Gate Extension for Improved Gate Control” International Journal of Advanced Computer Science and Applications(IJACSA), 10(1), 2019. http://dx.doi.org/10.14569/IJACSA.2019.0100125

@article{Mangesh2019,
title = {A Trapezoidal Cross-Section Stacked Gate FinFET with Gate Extension for Improved Gate Control},
journal = {International Journal of Advanced Computer Science and Applications},
doi = {10.14569/IJACSA.2019.0100125},
url = {http://dx.doi.org/10.14569/IJACSA.2019.0100125},
year = {2019},
publisher = {The Science and Information Organization},
volume = {10},
number = {1},
author = {Sangeeta Mangesh and Pradeep Chopra and Krishan K. Saini}
}