Abstract: Fault injection tools are designed to serve various purposes, such as validate the design under test concerning reli-ability requirements, find sensitive/critical locations that require error mitigation, determine the expected circuit response in the existence of faults. Fault Simulation/Emulation (S/E) applications are involved in Field Programmable Gate Array (FPGA) based design’s verification and simulation at the Hardware Description Languages (HDL) code level. A tool is developed, named RASP-FIT, to perform code modification of FPGA designs, testing of such designs, and finding the sensitive area of designs. This tool works on the FPGA designs written in Verilog HDL at various abstraction levels, gate, data-flow and behavioural levels. This paper presents a technical aspect and the user-guide for the proposed tool in detail, which includes generation of the standalone application (an executable file of the tool for Windows operating system) and installation method.

Abdul Rafay Khatri, “A Technical Guide for the RASP-FIT Tool” International Journal of Advanced Computer Science and Applications(IJACSA), 10(12), 2019. http://dx.doi.org/10.14569/IJACSA.2019.0101279

@article{Khatri2019,
title = {A Technical Guide for the RASP-FIT Tool},
journal = {International Journal of Advanced Computer Science and Applications},
doi = {10.14569/IJACSA.2019.0101279},
url = {http://dx.doi.org/10.14569/IJACSA.2019.0101279},
year = {2019},
publisher = {The Science and Information Organization},
volume = {10},
number = {12},
author = {Abdul Rafay Khatri}
}