Low Power and High Reliable Triple Modular Redundancy Latch for Single and Multi-node Upset Mitigation

CMOS based circuits are more susceptible to the radiation environment as the critical charge (Qcrit) decreases with technology scaling. A single ionizing radiation particle is more likely to upset the sensitive nodes of the circuit and causes Single Event Upset (SEU). Subsequently, hardening latches to transient faults at control inputs due to either single or multi-nodes is progressively important. This paper proposes a Fully Robust Triple Modular Redundancy (FRTMR) latch. In FRTMR latch, a novel majority voter circuit is proposed with a minimum number of sensitive nodes. It is highly immune to single and multi-node upsets. The proposed latch is implemented using CMOS 45 nm process and is simulated in cadence spectre environment. Results demonstrate that the proposed latch achieves 17.83 % low power and 13.88 % low area compared to existing Triple Modular Redundant (TMR) latch. The current induced due to transient fault occurrence at various sensitive nodes are exhibited with a double exponential current source for circuit simulation with a minimum threshold current value of 40 µA.

@article{Kumar2019,
  title     = {Low Power and High Reliable Triple Modular Redundancy Latch for Single and Multi-node Upset Mitigation},
  journal   = {International Journal of Advanced Computer Science and Applications},
  volume    = {10},
  number    = {7},
  year      = {2019},
  publisher = {The Science and Information Organization},
  author    = {S Satheesh Kumar and S Kumaravel},
  doi       = {10.14569/IJACSA.2019.0100760},
  url       = {https://doi.org/10.14569/IJACSA.2019.0100760}
}