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Article Details

Copyright Statement: This is an open access article licensed under a Creative Commons Attribution 4.0 International License, which permits unrestricted use, distribution, and reproduction in any medium, even commercially as long as the original work is properly cited.

Low Power and High Reliable Triple Modular Redundancy Latch for Single and Multi-node Upset Mitigation

Author 1: S Satheesh Kumar
Author 2: S Kumaravel

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Digital Object Identifier (DOI) : 10.14569/IJACSA.2019.0100760

Article Published in International Journal of Advanced Computer Science and Applications(IJACSA), Volume 10 Issue 7, 2019.

  • Abstract and Keywords
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Abstract: CMOS based circuits are more susceptible to the radiation environment as the critical charge (Qcrit) decreases with technology scaling. A single ionizing radiation particle is more likely to upset the sensitive nodes of the circuit and causes Single Event Upset (SEU). Subsequently, hardening latches to transient faults at control inputs due to either single or multi-nodes is progressively important. This paper proposes a Fully Robust Triple Modular Redundancy (FRTMR) latch. In FRTMR latch, a novel majority voter circuit is proposed with a minimum number of sensitive nodes. It is highly immune to single and multi-node upsets. The proposed latch is implemented using CMOS 45 nm process and is simulated in cadence spectre environment. Results demonstrate that the proposed latch achieves 17.83 % low power and 13.88 % low area compared to existing Triple Modular Redundant (TMR) latch. The current induced due to transient fault occurrence at various sensitive nodes are exhibited with a double exponential current source for circuit simulation with a minimum threshold current value of 40 µA.

Keywords: Multiple Event Transient (MET); Single Event Upset (SEU); Single Event Transient (SET); Radiation hardening; Reliability; Transient fault; Triple Modular Redundancy (TMR)

S Satheesh Kumar and S Kumaravel, “Low Power and High Reliable Triple Modular Redundancy Latch for Single and Multi-node Upset Mitigation” International Journal of Advanced Computer Science and Applications(IJACSA), 10(7), 2019. http://dx.doi.org/10.14569/IJACSA.2019.0100760

@article{Kumar2019,
title = {Low Power and High Reliable Triple Modular Redundancy Latch for Single and Multi-node Upset Mitigation},
journal = {International Journal of Advanced Computer Science and Applications},
doi = {10.14569/IJACSA.2019.0100760},
url = {http://dx.doi.org/10.14569/IJACSA.2019.0100760},
year = {2019},
publisher = {The Science and Information Organization},
volume = {10},
number = {7},
author = {S Satheesh Kumar and S Kumaravel}
}


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