Overview of Fault Tolerance Techniques and the Proposed TMR Generator Tool for FPGA Designs

The FPGA has been involved in many safety and mission-critical applications in the last few decades. FPGA designs are also critical to errors and failures due to radiations. Fault-tolerant systems should be designed to overcome the effect of faults or failure during the operation of the systems. The primary objective of any fault tolerance technique is to produce a dependable system. Fault tolerance techniques add the capability to perform proper functioning in the presence of a fault. Fault-tolerant techniques can detect the faults and correct them, or mask the faults. The overview of the most standard techniques used for FPGA designs is described in the paper. Among them, it is found that the Triple Modular Redundancy (TMR) technique is the most straight forward in terms of implementation and easy to use. The proposed TMR code generator for implementing the FPGA design is also described. These FPGA designs are written in Verilog Hardware Description Language (HDL) at the different abstraction levels.

@article{Khatri2020,
  title     = {Overview of Fault Tolerance Techniques and the Proposed TMR Generator Tool for FPGA Designs},
  journal   = {International Journal of Advanced Computer Science and Applications},
  volume    = {11},
  number    = {4},
  year      = {2020},
  publisher = {The Science and Information Organization},
  author    = {Abdul Rafay Khatri},
  doi       = {10.14569/IJACSA.2020.0110497},
  url       = {https://doi.org/10.14569/IJACSA.2020.0110497}
}