Design and Implementation of True Parallelism Quad-Engine Cybersecurity Architecture on FPGA

Applications, such as Internet of Things, deal with huge amount of transmitted, processed and stored images that required a high computing capability. Therefore, there is a need a computing architecture that contribute in increasing the throughput by exploiting modern technologies in both spatial and temporal parallelisms. This paper conducts a parallel quad-engine cybersecurity architecture with new configuration to increase the throughput. using DE1-SoC and Neek FPGA boards and HDL. In this architecture, each engine operates with 600MHz maximum frequency. Each image is divided into four parts of equal size and each part processed by single engine concurrently to achieve spatial parallelism. Internally, engine is handling image’s part in temporal parallelism and deep pipelining abstraction applied in every engine by dividing it to sub modules to execute different tasks concurrently. All data processed in engines is encrypted via AES algorithm that implemented as a significant part of engine architecture. The obtained results increased the throughput by four times, with 153,600Mbps, that make this computing architecture efficient and suitable for fast applications such as IoT and cybersecurity level of processing.

@article{Mohammed2022,
  title     = {Design and Implementation of True Parallelism Quad-Engine Cybersecurity Architecture on FPGA},
  journal   = {International Journal of Advanced Computer Science and Applications},
  volume    = {13},
  number    = {1},
  year      = {2022},
  publisher = {The Science and Information Organization},
  author    = {Nada Qaim Mohammed and Amiza Amir and Muataz Hammed Salih and Badlishah Ahmad},
  doi       = {10.14569/IJACSA.2022.0130183},
  url       = {https://doi.org/10.14569/IJACSA.2022.0130183}
}