An Efficiency Hardware Design for Lane Detector Systems

The Hough Transform (HT) algorithm is a popular method for lane detection based on the 'voting' process to extract complete lines. The voting process is derived from the HT algorithm and then executed in parameter space (ρ, θ) to identify the 'votes' with the highest count, meaning that image points with pairs of angle θ and distance ρ corresponding to those 'votes' lie on the same line. However, this algorithm requires significant memory and computational complexity. In this paper, we propose a new algorithm for the Hough Space (HS) by utilizing parameter-ization (Y-intercept, θ) instead of (ρ, θ) parameterization and lane direction. This simplifies the inverse LHT operation and reduces the accumulator's size and computational complexity compared to the standard LHT. We aim to minimize processing time per frame for real-time processing. Our implementation operates at a frequency of 250MHz, and the processing time for each frame with a resolution of 1024x1024 is 4.19ms, achieving an accuracy of 85.49%. This design is synthesized on the Virtex-7 VC707 FPGA.

@article{Lam2024,
  title     = {An Efficiency Hardware Design for Lane Detector Systems},
  journal   = {International Journal of Advanced Computer Science and Applications},
  volume    = {15},
  number    = {4},
  year      = {2024},
  publisher = {The Science and Information Organization},
  author    = {Duc Khai Lam},
  doi       = {10.14569/IJACSA.2024.01504118},
  url       = {https://doi.org/10.14569/IJACSA.2024.01504118}
}