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Research Article | Open Access |

RETRACTED: FPGA-Based Design of High-Speed CIC Decimator for Wireless Applications

Author 1: Rakjesh Mehra Author 2: Rashmi Arora
International Journal of Advanced Computer Science and Applications (IJACSA) · Vol. 2, No. 5 · Published 2011 · Cited by 12

DOI: 10.14569/IJACSA.2011.020510

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Abstract

After careful and considered review of the content of this paper by a duly constituted expert committee, this paper has been found to be in violation of IJACSA`s Publication Principles. We hereby retract the content of this paper. Reasonable effort should be made to remove all past references to this paper. Retraction DOI: 10.14569/IJACSA.2011.020510.retraction

Keywords

CIC FPGA FPGA GSM LUT SDR

How to Cite this Article

Mehra, R., & Arora, R. (2011). RETRACTED: FPGA-Based Design of High-Speed CIC Decimator for Wireless Applications. International Journal of Advanced Computer Science and Applications, 2(5). https://doi.org/10.14569/IJACSA.2011.020510

Mehra, Rakjesh, and Rashmi Arora. "RETRACTED: FPGA-Based Design of High-Speed CIC Decimator for Wireless Applications." International Journal of Advanced Computer Science and Applications, vol. 2, no. 5, 2011, https://doi.org/10.14569/IJACSA.2011.020510.

@article{Mehra2011,
  title     = {RETRACTED: FPGA-Based Design of High-Speed CIC Decimator for Wireless Applications},
  journal   = {International Journal of Advanced Computer Science and Applications},
  volume    = {2},
  number    = {5},
  year      = {2011},
  publisher = {The Science and Information Organization},
  author    = {Rakjesh Mehra and Rashmi Arora},
  doi       = {10.14569/IJACSA.2011.020510},
  url       = {https://doi.org/10.14569/IJACSA.2011.020510}
}

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