Abstract: Leakage power has become a serious concern in nanometer CMOS technologies. Dynamic and leakage power both are the main contributors to the total power consumption. In the past, the dynamic power has dominated the total power dissipation of CMOS devices. However, with the continuous trend of technology scaling, leakage power is becoming a main contributor to power consumption. In this paper, a technique has been proposed which will reduce simultaneously both glitch and leakage power. The results are simulated in Microwind3.1 in 90nm and 250 nm technology at room temperature.

Pushpa Saini and Rajesh Mehra, “A Novel Technique for Glitch and Leakage Power Reduction in CMOS VLSI Circuits” International Journal of Advanced Computer Science and Applications(IJACSA), 3(10), 2012. http://dx.doi.org/10.14569/IJACSA.2012.031026

@article{Saini2012,
title = {A Novel Technique for Glitch and Leakage Power Reduction in CMOS VLSI Circuits},
journal = {International Journal of Advanced Computer Science and Applications},
doi = {10.14569/IJACSA.2012.031026},
url = {http://dx.doi.org/10.14569/IJACSA.2012.031026},
year = {2012},
publisher = {The Science and Information Organization},
volume = {3},
number = {10},
author = {Pushpa Saini and Rajesh Mehra}
}