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An Improved Squaring Circuit for Binary Numbers
International Journal of Advanced Computer Science and Applications(IJACSA), Volume 3 Issue 2, 2012.
Abstract: In this paper, a high speed squaring circuit for binary numbers is proposed. High speed Vedic multiplier is used for design of the proposed squaring circuit. The key to our success is that only one Vedic multiplier is used instead of four multipliers reported in the literature. In addition, one squaring circuit is used twice. Our proposed Squaring Circuit seems to have better performance in terms of speed.
Keywords: Vedic mathematics; VLSI; binary multiplication; hardware design; VHDL.
Kabiraj Sethi and Rutuparna Panda. “An Improved Squaring Circuit for Binary Numbers”. International Journal of Advanced Computer Science and Applications (IJACSA) 3.2 (2012). http://dx.doi.org/10.14569/IJACSA.2012.030220
@article{Sethi2012,
title = {An Improved Squaring Circuit for Binary Numbers},
journal = {International Journal of Advanced Computer Science and Applications},
doi = {10.14569/IJACSA.2012.030220},
url = {http://dx.doi.org/10.14569/IJACSA.2012.030220},
year = {2012},
publisher = {The Science and Information Organization},
volume = {3},
number = {2},
author = {Kabiraj Sethi and Rutuparna Panda}
}
Copyright Statement: This is an open access article licensed under a Creative Commons Attribution 4.0 International License, which permits unrestricted use, distribution, and reproduction in any medium, even commercially as long as the original work is properly cited.
