DUT Verification Through an Efficient and Reusable Environment with Optimum Assertion and Functional Coverage in SystemVerilog
DOI: https://doi.org/10.14569/IJACSA.2014.050422
Abstract
Keywords
How to Cite this Article
Ahlawat, D., & Shukla, N. K. (2014). DUT Verification Through an Efficient and Reusable Environment with Optimum Assertion and Functional Coverage in SystemVerilog. International Journal of Advanced Computer Science and Applications, 5(4). https://doi.org/10.14569/IJACSA.2014.050422
Ahlawat, Deepika, and Neeraj Kr. Shukla. "DUT Verification Through an Efficient and Reusable Environment with Optimum Assertion and Functional Coverage in SystemVerilog." International Journal of Advanced Computer Science and Applications, vol. 5, no. 4, 2014, https://doi.org/10.14569/IJACSA.2014.050422.
@article{Ahlawat2014,
title = {DUT Verification Through an Efficient and Reusable Environment with Optimum Assertion and Functional Coverage in SystemVerilog},
journal = {International Journal of Advanced Computer Science and Applications},
volume = {5},
number = {4},
year = {2014},
publisher = {The Science and Information Organization},
author = {Deepika Ahlawat and Neeraj Kr. Shukla},
doi = {10.14569/IJACSA.2014.050422},
url = {https://doi.org/10.14569/IJACSA.2014.050422}
}
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