CPLD-Based Circuit Design of IGBT Dead-Time Compensation

IGBT (insulated-gate bipolar transistors) dead-time compensation circuit has a very important significant for improving the output voltage waveform of the inverter, reducing the harmonic output current. Thus, many compensation strategies are reported in literatures and have been implemented in industrial drives recently. Overall, the method of dead-time compensation can be divided into hardware compensation and software compensation. Hardware compensation method needs additional hardware circuits, which means additional space and cost. Still more, the additional circuit is easy to interfere with others, which can reduce the compensation accuracy. While the software compensation method takes up a lot of memory space and additional input-output ports of processor, which often result to the added operation and heat dissipation of controller. In this paper, CPLD (complex programmable logic device)-based circuit design of dead-time compensation is presented to solve these existed drawbacks. It is verified that not only can the circuit simplify existed inverter dead-time compensation design, but also it has the advantages of small volume, strong anti-interference ability, and high compensation precision. The simulation results validate that this method is feasible and effective.

@article{WANG2015,
  title     = {CPLD-Based Circuit Design of IGBT Dead-Time Compensation},
  journal   = {International Journal of Advanced Computer Science and Applications},
  volume    = {6},
  number    = {5},
  year      = {2015},
  publisher = {The Science and Information Organization},
  author    = {Qing-zhen WANG and Guo-hui ZENG and Jin LIU and Xing ZHAN},
  doi       = {10.14569/IJACSA.2015.060510},
  url       = {https://doi.org/10.14569/IJACSA.2015.060510}
}