An Integrated Architectural Clock Implemented Memory Design Analysis

Recently Low power consumption and Custom Memory design is major issue for embedded designer. Micro wind and Xilinx simulator implements SRAM design architecture and performs efficient simulation. These simulators implements high performances and low power consumption of SRAM design. SRAM efficiency analyzed with 6-T architecture design and row/column based architectural design. We have analyzed clock implemented memory design and simulated with specific application. We have implemented clock based SRAM architecture that improves the internal clock efficiency of SRAM. Architectural Clock implemented memory design reduces the propagation delay and access time. Internal semiconductor material design implemented technique also improves the SRAM data transitions scheme. Semiconductor material and clock implemented design improve simulation performance of SRAM and these design implements for recently developed Application Specific Memory Design Architecture and mobile devices.

@article{Khatwal2015,
  title     = {An Integrated Architectural Clock Implemented Memory Design Analysis},
  journal   = {International Journal of Advanced Computer Science and Applications},
  volume    = {6},
  number    = {7},
  year      = {2015},
  publisher = {The Science and Information Organization},
  author    = {Ravi Khatwal and Manoj Kumar Jain},
  doi       = {10.14569/IJACSA.2015.060717},
  url       = {https://doi.org/10.14569/IJACSA.2015.060717}
}