FSL-based Hardware Implementation for Parallel Computation of cDNA Microarray Image Segmentation

The present paper proposes a FPGA based hardware implementations for microarray image processing algorithms in order eliminate the shortcomings of the existing software platforms: user intervention, increased computation time and cost. The proposed image processing algorithms exclude user intervention from processing. An application-specific architecture is designed aiming microarray image processing algorithms parallelization in order to speed up computation. Hardware architectures for logarithm based image enhancement, profile computation and image segmentation are described. The methodology to integrate the hardware architecture within a microprocessor system is detailed. The Fast Simplex Link (FSL) bus is used to connect the hardware architecture as speed up co-processor of the microarray image processing system. Timing considerations were presented considering the levels of parallelism that can be achieved by using our proposed hardware architectures. The FPGA technology was chosen for implementation, due to its parallel computation capabilities and ease of reconfiguration.

@article{Bot2015,
  title     = {FSL-based Hardware Implementation for Parallel Computation of cDNA Microarray Image Segmentation},
  journal   = {International Journal of Advanced Computer Science and Applications},
  volume    = {6},
  number    = {7},
  year      = {2015},
  publisher = {The Science and Information Organization},
  author    = {Bogdan Bot and Simina Emerich and Sorin Martoiu and Bogdan Belean},
  doi       = {10.14569/IJACSA.2015.060704},
  url       = {https://doi.org/10.14569/IJACSA.2015.060704}
}