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International Journal of Advanced Computer Science and Applications(IJACSA), Volume 7 Issue 7, 2016.
Abstract: An Arithmetic Logic Unit (ALU) is the heart of every central processing unit (CPU) which performs basic operations like addition, subtraction, multiplication, division and bitwise logic operations on binary numbers. This paper deals with implementation of a basic ALU unit using two different types of adder circuits, a ripple carry adder and a sklansky type adder. The ALU is designed using application specific integrated circuit (ASIC) platform where VHDL hardware description language and standard cells are used. The target process technology is 130nm CMOS from the foundry ST Microelectronics. The Cadence EDA tools are used for the ASIC implementation. A comparative analysis is provided for the two ALU circuits designed in terms of area, power and timing requirements.
Abdul Rehman Buzdar, Liguo Sun and Abdullah Buzdar, “Comparative Analysis of ALU Implementation with RCA and Sklansky Adders In ASIC Design Flow” International Journal of Advanced Computer Science and Applications(IJACSA), 7(7), 2016. http://dx.doi.org/10.14569/IJACSA.2016.070767
@article{Buzdar2016,
title = {Comparative Analysis of ALU Implementation with RCA and Sklansky Adders In ASIC Design Flow},
journal = {International Journal of Advanced Computer Science and Applications},
doi = {10.14569/IJACSA.2016.070767},
url = {http://dx.doi.org/10.14569/IJACSA.2016.070767},
year = {2016},
publisher = {The Science and Information Organization},
volume = {7},
number = {7},
author = {Abdul Rehman Buzdar and Liguo Sun and Abdullah Buzdar}
}
Copyright Statement: This is an open access article licensed under a Creative Commons Attribution 4.0 International License, which permits unrestricted use, distribution, and reproduction in any medium, even commercially as long as the original work is properly cited.