Low Power Low Jitter 0.18 CMOS Ring VCO Design with Strategy based on EKV3.0 Model

In this paper, the design of micro-power CMOS ring VCO with minimum jitter intended for a concept of frequency synthesizer in biotelemetry systems is studied. A design procedure implemented in MATLAB is described for a circuit realization with TSMC 0.18µm CMOS technology. This conventional design methodology based on EKV3.0 model is clearly suited to the challenges of analog circuits design with reduced channel width. Measures realized with ADS confirmed methodology capability to circuit sizing respecting the specifications of application. The designed ring VCO operates at a central frequency of 433MHz in ISM band with an amplitude of oscillation equal to 500 mV. The integration area was intrinsic (without buffers and without external capacitances). The simulated phase noise is about -108 dBc/Hz at 1MHz, the value of rms jitter is 44.8 ps and the power consumption of the designed VCO is 6.37 mW @ 433 MHz.

@article{AYED2017,
  title     = {Low Power Low Jitter 0.18 CMOS Ring VCO Design with Strategy based on EKV3.0 Model},
  journal   = {International Journal of Advanced Computer Science and Applications},
  volume    = {8},
  number    = {12},
  year      = {2017},
  publisher = {The Science and Information Organization},
  author    = {Amine AYED and Hamadi GHARIANI},
  doi       = {10.14569/IJACSA.2017.081219},
  url       = {https://doi.org/10.14569/IJACSA.2017.081219}
}