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Copyright Statement: This is an open access article licensed under a Creative Commons Attribution 4.0 International License, which permits unrestricted use, distribution, and reproduction in any medium, even commercially as long as the original work is properly cited.
Cyclic Redundancy Checking (CRC) Accelerator for Embedded Processor Datapaths
Digital Object Identifier (DOI) : 10.14569/IJACSA.2017.080242
Article Published in International Journal of Advanced Computer Science and Applications(IJACSA), Volume 8 Issue 2, 2017.
Abstract: We present the integration of a multimode Cyclic Redundancy Checking (CRC) accelerator unit with an embedded processor datapath to enhance the processor performance in terms of execution time and energy efficiency. We investigate the performance of CRC accelerated embedded processor datapath in terms of execution time and energy efficiency. Our evaluation shows that the CRC accelerated Microblaze SoftCore embedded processor datapath is 153 times more cycle and energy efficient than a datapath lacking a CRC accelerator unit. This acceleration is achieved at the cost of some area overhead.
Keywords: CRC; Accelerator; Codesign; FPGA; MicroBlaze; Embedded Processor
Abdul Rehman Buzdar, Liguo Sun, Rao Kashif, Muhammad Waqar Azhar and Muhammad Imran Khan, “Cyclic Redundancy Checking (CRC) Accelerator for Embedded Processor Datapaths” International Journal of Advanced Computer Science and Applications(IJACSA), 8(2), 2017. http://dx.doi.org/10.14569/IJACSA.2017.080242
@article{Buzdar2017,
title = {Cyclic Redundancy Checking (CRC) Accelerator for Embedded Processor Datapaths},
journal = {International Journal of Advanced Computer Science and Applications},
doi = {10.14569/IJACSA.2017.080242},
url = {http://dx.doi.org/10.14569/IJACSA.2017.080242},
year = {2017},
publisher = {The Science and Information Organization},
volume = {8},
number = {2},
author = {Abdul Rehman Buzdar and Liguo Sun and Rao Kashif and Muhammad Waqar Azhar and Muhammad Imran Khan}
}
