Abstract: Viterbi algorithm is widely used in communication systems to efficiently decode the convolutional codes. This algorithm is used in many applications including cellular and satellite communication systems. Moreover, Serializer-deserializers (SERDESs) having critical latency constraint also use viterbi algorithm for hardware implementation. We present the integration of a mixed hardware/software viterbi accelerator unit with an embedded processor datapath to enhance the processor performance in terms of execution time and energy efficiency. Later we investigate the performance of viterbi accelerated embedded processor datapath in terms of execution time and energy efficiency. Our evaluation shows that the viterbi accelerated Microblaze soft-core embedded processor datapath is three times more cycle and energy efficient than a datapath lacking a viterbi accelerator unit. This acceleration is achieved at the cost of some area overhead.

Abdul Rehman Buzdar, Liguo Sun, Muhammad Waqar Azhar, Muhammad Imran Khan and Rao Kashif, “Area and Energy Efficient Viterbi Accelerator for Embedded Processor Datapaths” International Journal of Advanced Computer Science and Applications(IJACSA), 8(3), 2017. http://dx.doi.org/10.14569/IJACSA.2017.080355

@article{Buzdar2017,
title = {Area and Energy Efficient Viterbi Accelerator for Embedded Processor Datapaths},
journal = {International Journal of Advanced Computer Science and Applications}
doi = {10.14569/IJACSA.2017.080355},
url = {http://dx.doi.org/10.14569/IJACSA.2017.080355},
year = {2017},
publisher = {The Science and Information Organization},
volume = {8},
number = {3},
author = {Abdul Rehman Buzdar and Liguo Sun and Muhammad Waqar Azhar and Muhammad Imran Khan and Rao Kashif},
}