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VHDL Design and FPGA Implementation of LDPC Decoder for High Data Rate
Digital Object Identifier (DOI) : 10.14569/IJACSA.2017.080435
Article Published in International Journal of Advanced Computer Science and Applications(IJACSA), Volume 8 Issue 4, 2017.
Abstract: In this work, we present a FPGA design and implementation of a parallel architecture of a low complexity LDPC decoder for high data rate applications. The selected code is a regular LDPC code (3, 4). VHDL design and synthesis of such architecture uses the decoding by the algorithm of BP (Believe propagation) simplified "Min-Sum". The complexity of the proposed architecture was studied; it is 6335 LEs at a data rate of 2.12 Gbps for quantization of 8 bits at the second iteration. We also realized a platform based on a co-simulation on Simulink to validate performance in BER (Bit Error Rate) of our architecture.
Keywords: error correcting codes; LDPC codes; BP “Min-Sum”; VHDL language; FPGA
A. Boudaoud, M. El Haroussi and E. Abdelmounim, “VHDL Design and FPGA Implementation of LDPC Decoder for High Data Rate” International Journal of Advanced Computer Science and Applications(IJACSA), 8(4), 2017. http://dx.doi.org/10.14569/IJACSA.2017.080435
@article{Boudaoud2017,
title = {VHDL Design and FPGA Implementation of LDPC Decoder for High Data Rate},
journal = {International Journal of Advanced Computer Science and Applications},
doi = {10.14569/IJACSA.2017.080435},
url = {http://dx.doi.org/10.14569/IJACSA.2017.080435},
year = {2017},
publisher = {The Science and Information Organization},
volume = {8},
number = {4},
author = {A. Boudaoud and M. El Haroussi and E. Abdelmounim}
}
