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Research Article | Open Access |

VHDL Design and FPGA Implementation of LDPC Decoder for High Data Rate

Author 1: A. Boudaoud Author 2: M. El Haroussi Author 3: E. Abdelmounim
International Journal of Advanced Computer Science and Applications (IJACSA) · Vol. 8, No. 4 · Published 2017 · Cited by 5

DOI: https://doi.org/10.14569/IJACSA.2017.080435

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Abstract

In this work, we present a FPGA design and implementation of a parallel architecture of a low complexity LDPC decoder for high data rate applications. The selected code is a regular LDPC code (3, 4). VHDL design and synthesis of such architecture uses the decoding by the algorithm of BP (Believe propagation) simplified "Min-Sum". The complexity of the proposed architecture was studied; it is 6335 LEs at a data rate of 2.12 Gbps for quantization of 8 bits at the second iteration. We also realized a platform based on a co-simulation on Simulink to validate performance in BER (Bit Error Rate) of our architecture.

Keywords

error correcting codes LDPC codes BP “Min-Sum” VHDL language FPGA

How to Cite this Article

Boudaoud, A., Haroussi, M. E., & Abdelmounim, E. (2017). VHDL Design and FPGA Implementation of LDPC Decoder for High Data Rate. International Journal of Advanced Computer Science and Applications, 8(4). https://doi.org/10.14569/IJACSA.2017.080435

Boudaoud, A., et al.. "VHDL Design and FPGA Implementation of LDPC Decoder for High Data Rate." International Journal of Advanced Computer Science and Applications, vol. 8, no. 4, 2017, https://doi.org/10.14569/IJACSA.2017.080435.

@article{Boudaoud2017,
  title     = {VHDL Design and FPGA Implementation of LDPC Decoder for High Data Rate},
  journal   = {International Journal of Advanced Computer Science and Applications},
  volume    = {8},
  number    = {4},
  year      = {2017},
  publisher = {The Science and Information Organization},
  author    = {A. Boudaoud and M. El Haroussi and E. Abdelmounim},
  doi       = {10.14569/IJACSA.2017.080435},
  url       = {https://doi.org/10.14569/IJACSA.2017.080435}
}

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