A Bottom-up Approach for Visual Object Recognition on FPGA based Embedded Multiprocessor Architecture
DOI: 10.14569/IJACSA.2017.080557
Abstract
Keywords
How to Cite this Article
Chenini, H. (2017). A Bottom-up Approach for Visual Object Recognition on FPGA based Embedded Multiprocessor Architecture. International Journal of Advanced Computer Science and Applications, 8(5). https://doi.org/10.14569/IJACSA.2017.080557
Chenini, Hanen. "A Bottom-up Approach for Visual Object Recognition on FPGA based Embedded Multiprocessor Architecture." International Journal of Advanced Computer Science and Applications, vol. 8, no. 5, 2017, https://doi.org/10.14569/IJACSA.2017.080557.
@article{Chenini2017,
title = {A Bottom-up Approach for Visual Object Recognition on FPGA based Embedded Multiprocessor Architecture},
journal = {International Journal of Advanced Computer Science and Applications},
volume = {8},
number = {5},
year = {2017},
publisher = {The Science and Information Organization},
author = {Hanen Chenini},
doi = {10.14569/IJACSA.2017.080557},
url = {https://doi.org/10.14569/IJACSA.2017.080557}
}
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