Reduced-Latency and Area-Efficient Architecture for FPGA-Based Stochastic LDPC Decoders

This paper introduces a new field programmable gate array (FPGA) based stochastic low-density parity-check (LDPC) decoding process, to implement fully parallel LDPC-decoders. The proposed technique is designed to optimize the FPGA logic utilisation and to decrease the decoding latency. In order to reduce the complexity, the variable node (VN) output saturated-counter is removed and each VN internal memory is mapped only in one slice distributed RAM. Furthermore, an efficient VN initialization, using the channel input probability, is performed to improve the decoder convergence, without requiring additional resources. The Xilinx FPGA implementation shows that the proposed decoding approach reaches high performance along with reduction of logic utilisation, even for short codes. As a result, for a (200, 100) regular codes, a 57% reduction of the average decoding cycles is attained with an important bit error rate improvement, at Eb/N0 = 5.5dB. Additionally, a significant hardware reduction is achieved.

@article{Zerari2017,
  title     = {Reduced-Latency and Area-Efficient Architecture for FPGA-Based Stochastic LDPC Decoders},
  journal   = {International Journal of Advanced Computer Science and Applications},
  volume    = {8},
  number    = {7},
  year      = {2017},
  publisher = {The Science and Information Organization},
  author    = {Ghania Zerari and Abderrezak Guessoum},
  doi       = {10.14569/IJACSA.2017.080707},
  url       = {https://doi.org/10.14569/IJACSA.2017.080707}
}