Topology-Aware Mapping Techniques for Heterogeneous HPC Systems: A Systematic Survey

At the present time, the modern platforms of high-performance computing (HPC) consists of heterogeneous computing devices which are connected through complex hierarchical networks. Moreover, it is moving towards the Exascale era and which makes the number of nodes to increase as well as the number of cores within a node to increase. As a consequence, the communication costs and the data movement are increasing. Given that, the efficient topology-aware process mapping has become vital to efficiently optimize the data locality management in order to improve the system performance and energy consumption. It will also decrease the communication cost of the processes by matching the application virtual topology (exploited by the system for assigning the processes to the physical processor) to the target underlying hardware architecture called physical topology. Additionally, improving the locality problem which is one of the most challenging issues faced by the current parallel applications. In this survey paper, we have studied various topology-aware mapping techniques and algorithms.

@article{Alotaibi2018,
  title     = {Topology-Aware Mapping Techniques for Heterogeneous HPC Systems: A Systematic Survey},
  journal   = {International Journal of Advanced Computer Science and Applications},
  volume    = {9},
  number    = {10},
  year      = {2018},
  publisher = {The Science and Information Organization},
  author    = {Saad B. Alotaibi and Fathy alboraei},
  doi       = {10.14569/IJACSA.2018.091045},
  url       = {https://doi.org/10.14569/IJACSA.2018.091045}
}