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Copyright Statement: This is an open access article licensed under a Creative Commons Attribution 4.0 International License, which permits unrestricted use, distribution, and reproduction in any medium, even commercially as long as the original work is properly cited.
Pipeline Hazards Resolution for a New Programmable Instruction Set RISC Processor
Digital Object Identifier (DOI) : 10.14569/IJACSA.2018.091047
Article Published in International Journal of Advanced Computer Science and Applications(IJACSA), Volume 9 Issue 10, 2018.
Abstract: The work presented in this paper is a part of a project that aims to concept and implement a hardwired programmable processor. A 32-bit RISC processor with customizable ALU (Arithmetic and Logic Unit) is designed then the pipeline technique is implemented is order to reach better performances. However the use of this technique can lead to several troubles called hazards that can affect the correct execution of the program. In this context, this paper identifies and analyzes all different hazards that can occur in this processor pipeline stages. Then detailed solutions are proposed, implemented and validated.
Keywords: Processor; RISC; hardware; instruction set; pipeline; hazards; branch predictor; bypass
Hajer Najjar, Riad Bourguiba and Jaouhar Mouine, “Pipeline Hazards Resolution for a New Programmable Instruction Set RISC Processor” International Journal of Advanced Computer Science and Applications(IJACSA), 9(10), 2018. http://dx.doi.org/10.14569/IJACSA.2018.091047
@article{Najjar2018,
title = {Pipeline Hazards Resolution for a New Programmable Instruction Set RISC Processor},
journal = {International Journal of Advanced Computer Science and Applications}
doi = {10.14569/IJACSA.2018.091047},
url = {http://dx.doi.org/10.14569/IJACSA.2018.091047},
year = {2018},
publisher = {The Science and Information Organization},
volume = {9},
number = {10},
author = {Hajer Najjar and Riad Bourguiba and Jaouhar Mouine},
}
