An Efficient Fault Tolerance Technique for Through-Silicon-Vias in 3-D ICs

Three-dimensional integrated circuits (3D-ICs) based on Through-Silicon-Vias (TSVs) interconnection technology appeared as a viable solution to overcome problems of cost, reliability, yield and stacking area. In order to be commercially feasible, the 3D-IC yield must be as high as possible, which requires a tested and reparable TSVs. To overpass this challenge, an integration of interconnect built-in self-test (IBIST) methodology for 3D-IC is given in the aims to test the defectives TSVs. Once the interconnection has been tested, the result extracted from IBIST initiate the repairing defectives TSVs based on the built-in self-repair (BISR) structure. This paper superposed two fault tolerance techniques in particularly the redundant TSV and the time division multiplexing access (TDMA) in case of multi defectives TSV. This novel repair architecture increase the yield of 3D-ICs in a high failure rate. It leads to 100% reparability for 30% failure rate. A parallel processing approach of the proposed structure is presented to accelerate the test and repair operations. Achieved experimental results with the proposed methodology scheme show a good performance in terms of repair rate and yield.

@article{BENABDELADHIM2018,
  title     = {An Efficient Fault Tolerance Technique for Through-Silicon-Vias in 3-D ICs},
  journal   = {International Journal of Advanced Computer Science and Applications},
  volume    = {9},
  number    = {7},
  year      = {2018},
  publisher = {The Science and Information Organization},
  author    = {Mohamed BENABDELADHIM and Wael DGHAIS and Fakhreddine ZAYER and Belgacem HAMDI},
  doi       = {10.14569/IJACSA.2018.090737},
  url       = {https://doi.org/10.14569/IJACSA.2018.090737}
}