Copyright Statement: This is an open access article licensed under a Creative Commons Attribution 4.0 International License, which permits unrestricted use, distribution, and reproduction in any medium, even commercially as long as the original work is properly cited.
Digital Object Identifier (DOI) : 10.14569/IJACSA.2012.031118
Article Published in International Journal of Advanced Computer Science and Applications(IJACSA), Volume 3 Issue 11, 2012.
Abstract: This paper presents the design and simulations results of a switched-capacitor discrete time Second order Sigma-Delta modulator used for a resolution of 14 bits Sigma-Delta analog to digital converter. The use of operational amplifier is necessary for low power consumption, it is designed to provide large bandwidth and moderate DC gain. With 0.35µm CMOS technology, the S? modulator achieves 86 dB dynamic range, and 85 dB signal to noise ratio (SNR) over an 80 KHz signal bandwidth with an oversampling ratio (OSR) of 88, while dissipating 9.8mW at ±1.5V supply voltage.
Radwene LAAJIMI and Mohamed MASMOUDI, “Design of A high performance low-power consumption discrete time Second order Sigma-Delta modulator used for Analog to Digital Converter” International Journal of Advanced Computer Science and Applications(IJACSA), 3(11), 2012. http://dx.doi.org/10.14569/IJACSA.2012.031118