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DOI: 10.14569/IJACSA.2020.0110805
PDF

Development and Verification of Serial Fault Simulation for FPGA Designs using the Proposed RASP-FIT Tool

Author 1: Abdul Rafay Khatri
Author 2: Ali Hayek
Author 3: Josef Borcsok

International Journal of Advanced Computer Science and Applications(IJACSA), Volume 11 Issue 8, 2020.

  • Abstract and Keywords
  • How to Cite this Article
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Abstract: Fault simulation is the critical approach for many applications such as fault detection & diagnostics, test set quality measurement, generation of test vectors, circuit testability, and many others along with the help of fault injection technique. The fault simulation approach is divided into many types. The most straightforward approach among them is a serial fault simulation. In the simulation process, the circuit under test is faulted, and a faulty copy is achieved by either using a simulator command technique or instrumentation technique. A fault simulator must examine the behaviour of specified target fault in design and classified as detected or undetected by the applied test patterns. To modify the original code is a very challenging and time-consuming task. Therefore, the RASP-FIT tool is developed, which alters the fault-free FPGA design, which is under investigation, at the Verilog HDL code level. It produces the copies of faulty design along with the top design file for several fault simulation methods. Using this tool, a serial fault simulation environment can easily be created with no much effort. In this work, a serial fault simulation method is verified and validated using the RASP-FIT tool for an ISCAS’85 benchmark design as an example.

Keywords: FPGA design; fault injection; fault simulation; RASP-FIT tool; Verilog HDL

Abdul Rafay Khatri, Ali Hayek and Josef Borcsok, “Development and Verification of Serial Fault Simulation for FPGA Designs using the Proposed RASP-FIT Tool” International Journal of Advanced Computer Science and Applications(IJACSA), 11(8), 2020. http://dx.doi.org/10.14569/IJACSA.2020.0110805

@article{Khatri2020,
title = {Development and Verification of Serial Fault Simulation for FPGA Designs using the Proposed RASP-FIT Tool},
journal = {International Journal of Advanced Computer Science and Applications},
doi = {10.14569/IJACSA.2020.0110805},
url = {http://dx.doi.org/10.14569/IJACSA.2020.0110805},
year = {2020},
publisher = {The Science and Information Organization},
volume = {11},
number = {8},
author = {Abdul Rafay Khatri and Ali Hayek and Josef Borcsok}
}



Copyright Statement: This is an open access article licensed under a Creative Commons Attribution 4.0 International License, which permits unrestricted use, distribution, and reproduction in any medium, even commercially as long as the original work is properly cited.

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