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Article Details

Copyright Statement: This is an open access article licensed under a Creative Commons Attribution 4.0 International License, which permits unrestricted use, distribution, and reproduction in any medium, even commercially as long as the original work is properly cited.

Hardware Architecture for Adaptive Dual Threshold Filter and Discrete Wavelet Transform based ECG Signal Denoising

Author 1: Safa MEJHOUDI
Author 2: Rachid LATIF Wissam JENKAL
Author 3: Amine Saddik
Author 4: Abdelhafid EL OUARDI SATIE

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Digital Object Identifier (DOI) : 10.14569/IJACSA.2021.0121106

Article Published in International Journal of Advanced Computer Science and Applications(IJACSA), Volume 12 Issue 11, 2021.

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Abstract: The ECG signal, like all signals obtained when instrumenting a data acquisition system, is affected by noises of physiological and technical sources such as Electromyogram (EMG) and power line interferences, which can deteriorate its morphology. To overcome this issue, it’s subjected to apply a preprocessing step to remove these noises. Filtring techniques are complex computations becoming more common in medical applications, which must be completed in real-time. As a result, these applications are geared at integrating high-performance embedded architectures. This paper presents an FPGA (Field Programmable Gate Array) embedded architecture designed for an ECG denoising hybrid technique based on the Discrete Wavelet transform (DWT) and the Adaptive Dual Threshold Filter (ADTF), dedicated to handle with noises affecting ECG signals. The architecture was designed following a hardware-software codesign using a high-level description language and synthetized to be implemented on different FPGAs due to the structural description flexibility. The global architecture was divided into a set of functional blocks to allow parallel processing of ECG data. The simulation results confirm the high performance of the system in noise reduction without affecting the morphology of the signal. The process takes 0.3 ms with an acquisition frequency of 360 Hz. The whole architecture requires a small area in different FPGAs in terms of resources utilization. It uses less than 1% of the total registers for all FPGA devices which represents a total of 292 registers for Cyclone III LS, Cyclone IV GX, Cyclone IV E, and Arria II GX; and a total of 329 registers for Cyclone V. The logic elements occupancy varies between 3% using Cyclone V and 60% using Cyclone IV GX freeing up space for other parallel processing tasks.

Keywords: ECG signal; DWT; ADTF; hybrid technique; hardware-software codesign; FPGA

Safa MEJHOUDI, Rachid LATIF Wissam JENKAL, Amine Saddik and Abdelhafid EL OUARDI SATIE, “Hardware Architecture for Adaptive Dual Threshold Filter and Discrete Wavelet Transform based ECG Signal Denoising” International Journal of Advanced Computer Science and Applications(IJACSA), 12(11), 2021. http://dx.doi.org/10.14569/IJACSA.2021.0121106

@article{MEJHOUDI2021,
title = {Hardware Architecture for Adaptive Dual Threshold Filter and Discrete Wavelet Transform based ECG Signal Denoising},
journal = {International Journal of Advanced Computer Science and Applications},
doi = {10.14569/IJACSA.2021.0121106},
url = {http://dx.doi.org/10.14569/IJACSA.2021.0121106},
year = {2021},
publisher = {The Science and Information Organization},
volume = {12},
number = {11},
author = {Safa MEJHOUDI and Rachid LATIF Wissam JENKAL and Amine Saddik and Abdelhafid EL OUARDI SATIE}
}


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