Address Pattern Recognition Flash Translation Layer for Quadruple-level cell NAND-based Smart Devices

The price of the solid-state drives has become a major factor in the development of flash memory technology. Major semiconductor companies are developing quadruple-level cell NAND-based SSDs for smart devices. Unfortunately, SSDs composed of quadruple-level cell (QLC) flash memory may suffer from low performance. In addition, few studies on internal page buffering mechanisms have been conducted. As a solution to these problems, an address pattern recognition flash translation layer (APR-FTL) is proposed in this study. APRA-FTL gathers the data in a page unit and separates random data from sequential data. Furthermore, APRA-FTL proposes address mapping algorithm which is compatible to the page buffering algorithm. Experimental results show that APRA-FTL generates a lower number of write and erase operations compared to previous FTL algorithms.

@article{Kwon2022,
  title     = {Address Pattern Recognition Flash Translation Layer for Quadruple-level cell NAND-based Smart Devices},
  journal   = {International Journal of Advanced Computer Science and Applications},
  volume    = {13},
  number    = {10},
  year      = {2022},
  publisher = {The Science and Information Organization},
  author    = {Se Jin Kwon},
  doi       = {10.14569/IJACSA.2022.01310113},
  url       = {https://doi.org/10.14569/IJACSA.2022.01310113}
}