Abstract: Modern integrated circuit design manufacturing involves outsourcing intellectual property to third-party vendors to cut down on overall cost. Since there is a partial surrender of control, these third-party vendors may introduce malicious circuit commonly known as Hardware Trojan into the system in such a way that it goes undetected by the end-users’ default security measures. Therefore, to mitigate the threat of functionality change caused by the Trojan, a technique is proposed based on the testability measures in gate level netlists using Machine Learning. The proposed technique detects the presence of Trojan from the gate-level description of nodes using controllability and observability values. Various Machine Learning models are implemented to classify the nodes as Trojan infected and non-infected. The efficiency of linear discriminant analysis obtains an accuracy of 92.85 %, precision of 99.9 %, recall of 80%, and F1 score of 88.8% with a latency of around 0.9 ms.

Thejaswini P, Anu H, Aravind H S, D Mahesh Kumar, Syed Asif, Thirumalesh B, Pooja C A and Pavan G R, “Hardware Trojan Detection based on Testability Measures in Gate Level Netlists using Machine Learning” International Journal of Advanced Computer Science and Applications(IJACSA), 13(12), 2022. http://dx.doi.org/10.14569/IJACSA.2022.0131225

@article{P2022,
title = {Hardware Trojan Detection based on Testability Measures in Gate Level Netlists using Machine Learning},
journal = {International Journal of Advanced Computer Science and Applications},
doi = {10.14569/IJACSA.2022.0131225},
url = {http://dx.doi.org/10.14569/IJACSA.2022.0131225},
year = {2022},
publisher = {The Science and Information Organization},
volume = {13},
number = {12},
author = {Thejaswini P and Anu H and Aravind H S and D Mahesh Kumar and Syed Asif and Thirumalesh B and Pooja C A and Pavan G R}
}