Abstract: The five-stage pipeline processor is a mature and stable processor architecture suitable for many applications in the field of computer hardware. Based on the RISC-V instruction set architecture, the five-stage pipeline processor has advantages in performance, functionality, and power consumption. This paper presents an optimized RV32I five-stage pipeline processor, NRP, and proposes two optimization methods to improve the performance of NRP. These methods include instruction decoding unit optimization and branch prediction optimization. We implemented NRP using Verilog HDL and verified its performance using Vivado and the Xilinx Artya7-35T FPGA board. Experimental data shows that after adopting these methods, the CoreMark score of the five-stage pipeline processor reached 3.11 CoreMark/MHz, representing an 11.07% performance improvement.

Hongkui Li, Chaoxia Jing and Jie Liu, “Performance-Optimised Design of the RISC-V Five-Stage Pipelined Processor NRP” International Journal of Advanced Computer Science and Applications(IJACSA), 15(2), 2024. http://dx.doi.org/10.14569/IJACSA.2024.0150229

@article{Li2024,
title = {Performance-Optimised Design of the RISC-V Five-Stage Pipelined Processor NRP},
journal = {International Journal of Advanced Computer Science and Applications},
doi = {10.14569/IJACSA.2024.0150229},
url = {http://dx.doi.org/10.14569/IJACSA.2024.0150229},
year = {2024},
publisher = {The Science and Information Organization},
volume = {15},
number = {2},
author = {Hongkui Li and Chaoxia Jing and Jie Liu}
}